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Searched refs:HHI_HDMI_PLL_CNTL5 (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/gpu/drm/meson/
H A Dmeson_vclk.c104 #define HHI_HDMI_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */ macro
250 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980); in meson_venci_cvbs_clock_config()
263 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729); in meson_venci_cvbs_clock_config()
280 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x65771290); in meson_venci_cvbs_clock_config()
506 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980); in meson_hdmi_pll_set_params()
522 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729); in meson_hdmi_pll_set_params()
550 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, in meson_hdmi_pll_set_params()
555 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, in meson_hdmi_pll_set_params()
562 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x33771290); in meson_hdmi_pll_set_params()
/openbmc/u-boot/drivers/video/meson/
H A Dmeson_vclk.c74 #define HHI_HDMI_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */ macro
217 hhi_write(HHI_HDMI_PLL_CNTL5, 0x71486980); in meson_venci_cvbs_clock_config()
226 hhi_write(HHI_HDMI_PLL_CNTL5, 0x001fa729); in meson_venci_cvbs_clock_config()
406 hhi_write(HHI_HDMI_PLL_CNTL5, 0x71486980); in meson_hdmi_pll_set_params()
422 hhi_write(HHI_HDMI_PLL_CNTL5, 0x001fa729); in meson_hdmi_pll_set_params()
/openbmc/linux/drivers/clk/meson/
H A Dgxbb.h101 #define HHI_HDMI_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */ macro
H A Dg12a.h118 #define HHI_HDMI_PLL_CNTL5 0x334 macro
/openbmc/u-boot/arch/arm/include/asm/arch-meson/
H A Dclock-gx.h101 #define HHI_HDMI_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */ macro