Home
last modified time | relevance | path

Searched refs:HHI_HDMI_PLL_CNTL3 (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/drivers/video/meson/
H A Dmeson_vclk.c72 #define HHI_HDMI_PLL_CNTL3 0x328 /* 0xca offset in data sheet */ macro
215 hhi_write(HHI_HDMI_PLL_CNTL3, 0x0d5c5091); in meson_venci_cvbs_clock_config()
224 hhi_write(HHI_HDMI_PLL_CNTL3, 0xa6212844); in meson_venci_cvbs_clock_config()
404 hhi_write(HHI_HDMI_PLL_CNTL3, 0x0d5c5091); in meson_hdmi_pll_set_params()
420 hhi_write(HHI_HDMI_PLL_CNTL3, 0x860f30c4); in meson_hdmi_pll_set_params()
441 hhi_update_bits(HHI_HDMI_PLL_CNTL3, in meson_hdmi_pll_set_params()
449 hhi_update_bits(HHI_HDMI_PLL_CNTL3, in meson_hdmi_pll_set_params()
457 hhi_update_bits(HHI_HDMI_PLL_CNTL3, in meson_hdmi_pll_set_params()
/openbmc/linux/drivers/gpu/drm/meson/
H A Dmeson_vclk.c102 #define HHI_HDMI_PLL_CNTL3 0x328 /* 0xca offset in data sheet */ macro
248 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091); in meson_venci_cvbs_clock_config()
261 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0xa6212844); in meson_venci_cvbs_clock_config()
278 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x00000000); in meson_venci_cvbs_clock_config()
504 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091); in meson_hdmi_pll_set_params()
520 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4); in meson_hdmi_pll_set_params()
543 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x00000000); in meson_hdmi_pll_set_params()
591 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3, in meson_hdmi_pll_set_params()
602 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3, in meson_hdmi_pll_set_params()
613 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3, in meson_hdmi_pll_set_params()
/openbmc/linux/drivers/clk/meson/
H A Dgxbb.h99 #define HHI_HDMI_PLL_CNTL3 0x328 /* 0xca offset in data sheet */ macro
H A Dg12a.h116 #define HHI_HDMI_PLL_CNTL3 0x32c macro
/openbmc/u-boot/arch/arm/include/asm/arch-meson/
H A Dclock-gx.h99 #define HHI_HDMI_PLL_CNTL3 0x328 /* 0xca offset in data sheet */ macro