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Searched refs:HHI_HDMI_CLK_CNTL (Results 1 – 11 of 11) sorted by relevance

/openbmc/u-boot/drivers/video/meson/
H A Dmeson_vclk.c63 #define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 offset in data sheet */ macro
601 hhi_update_bits(HHI_HDMI_CLK_CNTL, in meson_vclk_set()
603 hhi_update_bits(HHI_HDMI_CLK_CNTL, in meson_vclk_set()
605 hhi_update_bits(HHI_HDMI_CLK_CNTL, in meson_vclk_set()
661 hhi_update_bits(HHI_HDMI_CLK_CNTL, in meson_vclk_set()
670 hhi_update_bits(HHI_HDMI_CLK_CNTL, in meson_vclk_set()
680 hhi_update_bits(HHI_HDMI_CLK_CNTL, in meson_vclk_set()
690 hhi_update_bits(HHI_HDMI_CLK_CNTL, in meson_vclk_set()
700 hhi_update_bits(HHI_HDMI_CLK_CNTL, in meson_vclk_set()
H A Dmeson_dw_hdmi.c35 #define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 */ macro
262 dw_hdmi_hhi_update_bits(priv, HHI_HDMI_CLK_CNTL, 0xffff, 0x100); in meson_dw_hdmi_phy_init()
385 dw_hdmi_hhi_update_bits(priv, HHI_HDMI_CLK_CNTL, 0xffff, 0x100); in meson_dw_hdmi_probe()
/openbmc/linux/drivers/gpu/drm/meson/
H A Dmeson_vclk.c89 #define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 offset in data sheet */ macro
817 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
819 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
821 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
898 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
907 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
916 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
925 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
934 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
H A Dmeson_dw_hdmi.c106 #define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 */ macro
617 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100); in meson_dw_hdmi_init()
/openbmc/linux/drivers/clk/meson/
H A Dmeson8b.h45 #define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 offset in data sheet */ macro
H A Dgxbb.h57 #define HHI_HDMI_CLK_CNTL 0x1CC /* 0x73 offset in data sheet */ macro
H A Dg12a.h74 #define HHI_HDMI_CLK_CNTL 0x1CC macro
H A Dgxbb.c2319 .offset = HHI_HDMI_CLK_CNTL,
2414 .offset = HHI_HDMI_CLK_CNTL,
2430 .offset = HHI_HDMI_CLK_CNTL,
2445 .offset = HHI_HDMI_CLK_CNTL,
H A Dmeson8b.c1708 .offset = HHI_HDMI_CLK_CNTL,
1809 .offset = HHI_HDMI_CLK_CNTL,
1830 .offset = HHI_HDMI_CLK_CNTL,
1847 .offset = HHI_HDMI_CLK_CNTL,
H A Dg12a.c3585 .offset = HHI_HDMI_CLK_CNTL,
3736 .offset = HHI_HDMI_CLK_CNTL,
3752 .offset = HHI_HDMI_CLK_CNTL,
3767 .offset = HHI_HDMI_CLK_CNTL,
/openbmc/u-boot/arch/arm/include/asm/arch-meson/
H A Dclock-gx.h56 #define HHI_HDMI_CLK_CNTL 0x1CC /* 0x73 offset in data sheet */ macro