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Searched refs:HDP_HWIP (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dhdp_v4_0.c54 if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 4, 0) || in hdp_v4_0_invalidate_hdp()
55 adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 4, 2)) in hdp_v4_0_invalidate_hdp()
87 if (adev->ip_versions[HDP_HWIP][0] >= IP_VERSION(4, 4, 0)) in hdp_v4_0_reset_ras_error_count()
99 if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 0, 0) || in hdp_v4_0_update_clock_gating()
100 adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 0, 1) || in hdp_v4_0_update_clock_gating()
101 adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 1, 1) || in hdp_v4_0_update_clock_gating()
102 adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 1, 0)) { in hdp_v4_0_update_clock_gating()
144 switch (adev->ip_versions[HDP_HWIP][0]) { in hdp_v4_0_init_registers()
154 if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 4, 0)) in hdp_v4_0_init_registers()
H A Ddimgrey_cavefish_reg_init.c36 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
H A Daldebaran_reg_init.c35 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in aldebaran_reg_base_init()
H A Darct_reg_init.c35 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in arct_reg_base_init()
H A Damdgpu_discovery.c182 [HDP_HWIP] = HDP_HWID,
2166 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); in amdgpu_discovery_set_ip_blocks()
2188 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); in amdgpu_discovery_set_ip_blocks()
2212 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); in amdgpu_discovery_set_ip_blocks()
2228 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); in amdgpu_discovery_set_ip_blocks()
2249 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); in amdgpu_discovery_set_ip_blocks()
2273 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); in amdgpu_discovery_set_ip_blocks()
2301 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); in amdgpu_discovery_set_ip_blocks()
2465 switch (adev->ip_versions[HDP_HWIP][0]) { in amdgpu_discovery_set_ip_blocks()
H A Dvega10_reg_init.c35 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in vega10_reg_base_init()
H A Dvega20_reg_init.c35 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in vega20_reg_base_init()
H A Damdgpu.h637 HDP_HWIP, enumerator