Searched refs:HDMI_CTL_3 (Results 1 – 2 of 2) sorted by relevance
47 mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_HDMITX_REF_XTAL_SEL); in mtk_hdmi_pll_sel_src()48 mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_HDMITX_REF_RESPLL_SEL); in mtk_hdmi_pll_sel_src()197 mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_PIXEL_CLOCK_SEL); in mtk_hdmi_pll_set_hw()200 mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_HDMITX_PIXEL_CLOCK); in mtk_hdmi_pll_set_hw()202 mtk_phy_set_bits(regs + HDMI_CTL_3, REG_HDMITX_PIXEL_CLOCK); in mtk_hdmi_pll_set_hw()203 mtk_phy_update_field(regs + HDMI_CTL_3, REG_HDMITXPLL_DIV, digital_div - 1); in mtk_hdmi_pll_set_hw()
106 #define HDMI_CTL_3 0xcc macro