| /openbmc/u-boot/include/dt-bindings/clock/ |
| H A D | rv1108-cru.h | 167 #define HCLK_VPU 345 macro
169 #define CLK_NR_CLKS (HCLK_VPU + 1)
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| H A D | rk3328-cru.h | 185 #define HCLK_VPU 426 macro
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| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | rv1108-cru.h | 164 #define HCLK_VPU 345 macro
166 #define CLK_NR_CLKS (HCLK_VPU + 1)
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| H A D | rk3228-cru.h | 133 #define HCLK_VPU 464 macro
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| H A D | px30-cru.h | 120 #define HCLK_VPU 244 macro
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| H A D | rk3328-cru.h | 188 #define HCLK_VPU 326 macro
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| H A D | rockchip,rk3588-cru.h | 449 #define HCLK_VPU 434 macro
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| H A D | rk3568-cru.h | 302 #define HCLK_VPU 239 macro
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| /openbmc/linux/arch/arm/boot/dts/rockchip/ |
| H A D | rk322x.dtsi | 228 <&cru HCLK_VPU>;
621 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
631 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
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| /openbmc/linux/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3328.dtsi | 320 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
643 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
654 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
664 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
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| H A D | px30.dtsi | 309 <&cru HCLK_VPU>,
1107 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1117 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
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| H A D | rk356x.dtsi | 601 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
612 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
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| /openbmc/linux/drivers/clk/rockchip/ |
| H A D | clk-rk3228.c | 632 GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 1, GFLAGS),
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| H A D | clk-rk3328.c | 529 GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", CLK_SET_RATE_PARENT,
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| H A D | clk-rv1108.c | 258 GATE(HCLK_VPU, "hclk_vpu", "hclk_rkvdec_pre", 0,
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| H A D | clk-px30.c | 873 GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0, PX30_CLKGATE_CON(4), 6, GFLAGS),
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| H A D | clk-rk3568.c | 1091 GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0,
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| H A D | clk-rk3588.c | 1729 GATE(HCLK_VPU, "hclk_vpu", "hclk_vdpu_root", 0,
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