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Searched refs:GPC_IPS_BASE_ADDR (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/arm/mach-imx/mx7/
H A Dpsci-mx7.c146 writel(enable, GPC_IPS_BASE_ADDR + offset); in imx_gpcv2_set_m_core_pgc()
159 val = readl(GPC_IPS_BASE_ADDR + reg); in imx_gpcv2_set_core_power()
161 writel(val, GPC_IPS_BASE_ADDR + reg); in imx_gpcv2_set_core_power()
163 while ((readl(GPC_IPS_BASE_ADDR + reg) & pdn_pup_req) != 0) in imx_gpcv2_set_core_power()
328 val1 = readl(GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC); in imx_gpcv2_set_lpm_mode()
329 val2 = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR); in imx_gpcv2_set_lpm_mode()
351 val3 = readl(GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0); in imx_gpcv2_set_lpm_mode()
353 writel(val3, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0); in imx_gpcv2_set_lpm_mode()
358 val3 = readl(GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0); in imx_gpcv2_set_lpm_mode()
360 writel(val3, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0); in imx_gpcv2_set_lpm_mode()
[all …]
H A Dsoc.c209 writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4); in imx_gpcv2_init()
210 writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE1 + i * 4); in imx_gpcv2_init()
211 writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_M4 + i * 4); in imx_gpcv2_init()
216 GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING); in imx_gpcv2_init()
219 val = readl(GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC); in imx_gpcv2_init()
221 writel(val, GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC); in imx_gpcv2_init()
224 val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_C0_PUPSCR); in imx_gpcv2_init()
227 writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_C0_PUPSCR); in imx_gpcv2_init()
230 val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_C1_PUPSCR); in imx_gpcv2_init()
233 writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_C1_PUPSCR); in imx_gpcv2_init()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx7/
H A Dimx-regs.h116 #define GPC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1A0000) macro