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Searched refs:GICR_ICPENDR0 (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/Documentation/virt/kvm/devices/
H A Darm-vgic-v3.rst99 GICR_ISPENDR0, GICD_ICPENDR, and GICR_ICPENDR0. These registers behave
159 Accesses to GICD_ICPENDR register region and GICR_ICPENDR0 registers have
/openbmc/qemu/hw/intc/
H A Darm_gicv3_redist.c396 case GICR_ICPENDR0: in gicr_readl()
555 case GICR_ICPENDR0: in gicr_writel()
H A Dgicv3_internal.h107 #define GICR_ICPENDR0 (GICR_SGI_OFFSET + 0x0280) macro
H A Darm_gicv3_kvm.c390 kvm_gicr_access(s, GICR_ICPENDR0, ncpu, &reg, true); in kvm_arm_gicv3_put()
/openbmc/linux/include/linux/irqchip/
H A Darm-gic-v3.h234 #define GICR_ICPENDR0 GICD_ICPENDR macro
/openbmc/linux/arch/arm64/kvm/vgic/
H A Dvgic-mmio-v3.c731 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICPENDR0,