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Searched refs:GG82563_REG (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/drivers/net/ethernet/intel/e1000e/
H A Ddefines.h769 #define GG82563_REG(page, reg) \ macro
775 GG82563_REG(0, 16) /* PHY Specific Control */
777 GG82563_REG(0, 22) /* Page Select */
779 GG82563_REG(0, 26) /* PHY Specific Control 2 */
781 GG82563_REG(0, 29) /* Alternate Page Select */
784 GG82563_REG(2, 21) /* MAC Specific Control Register */
787 GG82563_REG(5, 26) /* DSP Distance */
791 GG82563_REG(193, 16) /* Kumeran Mode Control */
793 GG82563_REG(193, 20) /* Power Management Control */
797 GG82563_REG(194, 18) /* Inband Control */
H A D80003es2lan.c1037 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4), in e1000_setup_copper_link_80003es2lan()
1041 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), in e1000_setup_copper_link_80003es2lan()
1046 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), in e1000_setup_copper_link_80003es2lan()
/openbmc/u-boot/drivers/net/
H A De1000.h2144 #define GG82563_REG(page, reg) \ macro
2150 GG82563_REG(0, 16) /* PHY Specific Control */
2152 GG82563_REG(0, 17) /* PHY Specific Status */
2154 GG82563_REG(0, 18) /* Interrupt Enable */
2156 GG82563_REG(0, 19) /* PHY Specific Status 2 */
2158 GG82563_REG(0, 21) /* Receive Error Counter */
2160 GG82563_REG(0, 22) /* Page Select */
2162 GG82563_REG(0, 26) /* PHY Specific Control 2 */
2164 GG82563_REG(0, 29) /* Alternate Page Select */
2166 GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */
[all …]
H A De1000.c3250 GG82563_REG(0x34, 4), 0xFFFF); in e1000_setup_copper_link()
3254 GG82563_REG(0x34, 9), &reg_data); in e1000_setup_copper_link()
3259 GG82563_REG(0x34, 9), reg_data); in e1000_setup_copper_link()