Home
last modified time | relevance | path

Searched refs:GEN8_L3SQCREG4 (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dintel_workarounds.c1976 whitelist_mcr_reg(w, GEN8_L3SQCREG4); in skl_whitelist_build()
1997 whitelist_mcr_reg(w, GEN8_L3SQCREG4); in kbl_whitelist_build()
2438 GEN8_L3SQCREG4, in rcs_engine_wa_init()
2567 GEN8_L3SQCREG4, in rcs_engine_wa_init()
2573 wa_mcr_write_clr_set(wal, GEN8_L3SQCREG4, in rcs_engine_wa_init()
H A Dintel_lrc.c1550 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); in gen8_emit_flush_coherentl3_wa()
1556 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); in gen8_emit_flush_coherentl3_wa()
1565 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); in gen8_emit_flush_coherentl3_wa()
H A Dintel_gt_regs.h1026 #define GEN8_L3SQCREG4 MCR_REG(0xb118) macro
/openbmc/linux/drivers/gpu/drm/i915/
H A Dintel_gvt_mmio_table.c829 MMIO_D(GEN8_L3SQCREG4); in iterate_bdw_plus_mmio()
/openbmc/linux/drivers/gpu/drm/i915/gvt/
H A Dcmd_parser.c923 if (offset == i915_mmio_reg_offset(GEN8_L3SQCREG4) || in cmd_reg_handler()
H A Dhandlers.c2546 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()