Home
last modified time | relevance | path

Searched refs:GEN7_MISCCPCTL (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/gpu/drm/i915/
H A Dintel_clock_gating.c334 misccpctl = intel_uncore_rmw(&i915->uncore, GEN7_MISCCPCTL, in gen8_set_l3sqc_credits()
349 intel_uncore_write(&i915->uncore, GEN7_MISCCPCTL, misccpctl); in gen8_set_l3sqc_credits()
479 intel_uncore_rmw(&i915->uncore, GEN7_MISCCPCTL, in skl_init_clock_gating()
H A Dvlv_suspend.c148 s->misccpctl = intel_uncore_read(uncore, GEN7_MISCCPCTL); in vlv_save_gunit_s0ix_state()
233 intel_uncore_write(uncore, GEN7_MISCCPCTL, s->misccpctl); in vlv_restore_gunit_s0ix_state()
H A Di915_irq.c196 misccpctl = intel_uncore_rmw(&dev_priv->uncore, GEN7_MISCCPCTL, in ivb_parity_work()
198 intel_uncore_posting_read(&dev_priv->uncore, GEN7_MISCCPCTL); in ivb_parity_work()
240 intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl); in ivb_parity_work()
H A Di915_perf.c2426 intel_uncore_rmw(uncore, GEN7_MISCCPCTL, in hsw_enable_metric_set()
2442 intel_uncore_rmw(uncore, GEN7_MISCCPCTL, in hsw_disable_metric_set()
H A Dintel_gvt_mmio_table.c801 MMIO_D(GEN7_MISCCPCTL); in iterate_bdw_plus_mmio()
/openbmc/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_fw.c43 intel_uncore_rmw(uncore, GEN7_MISCCPCTL, 0, in guc_prepare_xfer()
/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dintel_workarounds.c1501 wa_add(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE, in gen12_gt_workarounds_init()
1611 wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); in dg2_gt_workarounds_init()
1633 wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); in pvc_gt_workarounds_init()
1661 wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); in xelpg_gt_workarounds_init()
H A Dintel_gt_regs.h699 #define GEN7_MISCCPCTL _MMIO(0x9424) macro