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Searched refs:GATE_TOP2 (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt8167.c733 #define GATE_TOP2(_id, _name, _parent, _shift) \ macro
789 GATE_TOP2(CLK_TOP_MSDC2, "msdc2", "ahb_infra_sel", 0),
790 GATE_TOP2(CLK_TOP_RBIST, "rbist", "univpll_d12", 1),
791 GATE_TOP2(CLK_TOP_NFI_BUS, "nfi_bus", "ahb_infra_sel", 2),
792 GATE_TOP2(CLK_TOP_GCE, "gce", "ahb_infra_sel", 4),
793 GATE_TOP2(CLK_TOP_TRNG, "trng", "ahb_infra_sel", 5),
794 GATE_TOP2(CLK_TOP_SEJ_13M, "sej_13m", "clk26m_ck", 6),
795 GATE_TOP2(CLK_TOP_AES, "aes", "ahb_infra_sel", 7),
796 GATE_TOP2(CLK_TOP_PWM_B, "pwm_b", "rg_pwm_infra", 8),
797 GATE_TOP2(CLK_TOP_PWM1_FB, "pwm1_fb", "rg_pwm_infra", 9),
[all …]
H A Dclk-mt8516.c532 #define GATE_TOP2(_id, _name, _parent, _shift) \ macro
580 GATE_TOP2(CLK_TOP_MSDC2, "msdc2", "ahb_infra_sel", 0),
581 GATE_TOP2(CLK_TOP_RBIST, "rbist", "univpll_d12", 1),
582 GATE_TOP2(CLK_TOP_NFI_BUS, "nfi_bus", "ahb_infra_sel", 2),
583 GATE_TOP2(CLK_TOP_GCE, "gce", "ahb_infra_sel", 4),
584 GATE_TOP2(CLK_TOP_TRNG, "trng", "ahb_infra_sel", 5),
585 GATE_TOP2(CLK_TOP_SEJ_13M, "sej_13m", "clk26m_ck", 6),
586 GATE_TOP2(CLK_TOP_AES, "aes", "ahb_infra_sel", 7),
587 GATE_TOP2(CLK_TOP_PWM_B, "pwm_b", "rg_pwm_infra", 8),
588 GATE_TOP2(CLK_TOP_PWM1_FB, "pwm1_fb", "rg_pwm_infra", 9),
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H A Dclk-mt8365.c599 #define GATE_TOP2(_id, _name, _parent, _shift) \ macro
614 GATE_TOP2(CLK_TOP_AUD_I2S0_M, "aud_i2s0_m_ck", "apll12_ck_div0", 0),
615 GATE_TOP2(CLK_TOP_AUD_I2S1_M, "aud_i2s1_m_ck", "apll12_ck_div1", 1),
616 GATE_TOP2(CLK_TOP_AUD_I2S2_M, "aud_i2s2_m_ck", "apll12_ck_div2", 2),
617 GATE_TOP2(CLK_TOP_AUD_I2S3_M, "aud_i2s3_m_ck", "apll12_ck_div3", 3),
618 GATE_TOP2(CLK_TOP_AUD_TDMOUT_M, "aud_tdmout_m_ck", "apll12_ck_div4", 4),
619 GATE_TOP2(CLK_TOP_AUD_TDMOUT_B, "aud_tdmout_b_ck", "apll12_ck_div4b", 5),
620 GATE_TOP2(CLK_TOP_AUD_TDMIN_M, "aud_tdmin_m_ck", "apll12_ck_div5", 6),
621 GATE_TOP2(CLK_TOP_AUD_TDMIN_B, "aud_tdmin_b_ck", "apll12_ck_div5b", 7),
622 GATE_TOP2(CLK_TOP_AUD_SPDIF_M, "aud_spdif_m_ck", "apll12_ck_div6", 8),
H A Dclk-mt6765.c494 #define GATE_TOP2(_id, _name, _parent, _shift) \ macro
516 GATE_TOP2(CLK_TOP_APLL12_DIV0, "apll12_div0", "aud_1_ck", 2),
517 GATE_TOP2(CLK_TOP_APLL12_DIV1, "apll12_div1", "aud_1_ck", 3),
518 GATE_TOP2(CLK_TOP_APLL12_DIV2, "apll12_div2", "aud_1_ck", 4),
519 GATE_TOP2(CLK_TOP_APLL12_DIV3, "apll12_div3", "aud_1_ck", 5),