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Searched refs:FSYS1_MMC0_DIV_VAL (Results 1 – 1 of 1) sorted by relevance

/openbmc/u-boot/arch/arm/mach-exynos/
H A Dclock_init_exynos5.c21 #define FSYS1_MMC0_DIV_VAL 0x0701 macro
1000 div_mmc |= FSYS1_MMC0_DIV_VAL; in emmc_boot_clk_div_set()