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Searched refs:FSL_SRDSCR1_PLLBW (Results 1 – 1 of 1) sorted by relevance

/openbmc/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dserdes.c26 #define FSL_SRDSCR1_PLLBW 0x00000040 macro
83 tmp &= ~FSL_SRDSCR1_PLLBW; in fsl_setup_serdes()
106 tmp |= FSL_SRDSCR1_PLLBW; in fsl_setup_serdes()
128 tmp &= ~FSL_SRDSCR1_PLLBW; in fsl_setup_serdes()