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Searched refs:FPSR_NZCV_MASK (Results 1 – 5 of 5) sorted by relevance

/openbmc/qemu/target/arm/tcg/
H A Dtranslate-m-nocp.c343 tcg_gen_andi_i32(tmp, tmp, FPSR_NZCV_MASK); in gen_M_fp_sysreg_write()
345 tcg_gen_andi_i32(fpscr, fpscr, ~FPSR_NZCV_MASK); in gen_M_fp_sysreg_write()
393 tcg_gen_andi_i32(tmp, tmp, ~FPSR_NZCV_MASK); in gen_M_fp_sysreg_write()
469 tcg_gen_andi_i32(tmp, tmp, FPSR_NZCV_MASK); in gen_M_fp_sysreg_read()
479 tcg_gen_andi_i32(tmp, tmp, ~FPSR_NZCV_MASK); in gen_M_fp_sysreg_read()
532 tcg_gen_andi_i32(tmp, fpscr, ~FPSR_NZCV_MASK); in gen_M_fp_sysreg_read()
H A Dtranslate-vfp.c837 tcg_gen_andi_i32(tmp, tmp, FPSR_NZCV_MASK); in trans_VMSR_VMRS()
H A Dmve_helper.c1118 env->vfp.fpsr &= ~FPSR_NZCV_MASK; in DO_2OP_S()
/openbmc/qemu/target/arm/
H A Dvfp_helper.c214 val &= FPSR_NZCV_MASK | FPSR_CEXC_MASK; in vfp_set_fpsr()
1154 env->vfp.fpsr = (env->vfp.fpsr & ~FPSR_NZCV_MASK) | (z * FPSR_Z); in HELPER()
H A Dcpu.h1746 #define FPSR_NZCV_MASK (FPSR_N | FPSR_Z | FPSR_C | FPSR_V) macro
1747 #define FPSR_NZCVQC_MASK (FPSR_NZCV_MASK | FPSR_QC)