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Searched refs:FCSR0_M1 (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/target/loongarch/tcg/insn_trans/
H A Dtrans_fmov.c.inc7 UINT32_MAX, FCSR0_M1, FCSR0_M2, FCSR0_M3
/openbmc/qemu/target/loongarch/
H A Dcpu.h43 #define FCSR0_M1 0x1f /* FCSR1 mask, Enables */ macro
H A Dcpu.c521 env->fcsr0_mask = FCSR0_M1 | FCSR0_M2 | FCSR0_M3; in loongarch_cpu_reset_hold()