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Searched refs:FCR0_REV (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/target/mips/
H A Dcpu-defs.c.inc500 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
541 (1 << FCR0_S) | (0x02 << FCR0_PRID) | (0x0 << FCR0_REV),
564 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
585 .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
632 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
661 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
690 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
737 (0x89 << FCR0_PRID) | (0x0 << FCR0_REV),
774 (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV),
814 (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV),
[all …]
H A Dcpu.h63 #define FCR0_REV 0 macro