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Searched refs:ENABLE_L2_CACHE (Results 1 – 25 of 30) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v1_0.c180 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v1_0_init_cache_regs()
366 WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v1_0_gart_disable()
H A Dgfxhub_v2_0.c215 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v2_0_init_cache_regs()
381 WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v2_0_gart_disable()
H A Dgfxhub_v3_0_3.c222 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v3_0_3_init_cache_regs()
393 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v3_0_3_gart_disable()
H A Dgfxhub_v3_0.c217 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v3_0_init_cache_regs()
400 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v3_0_gart_disable()
H A Dmmhub_v3_0_2.c235 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v3_0_2_init_cache_regs()
411 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); in mmhub_v3_0_2_gart_disable()
H A Dmmhub_v3_0_1.c236 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v3_0_1_init_cache_regs()
406 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); in mmhub_v3_0_1_gart_disable()
H A Dmmhub_v2_3.c210 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v2_3_init_cache_regs()
394 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); in mmhub_v2_3_gart_disable()
H A Dmmhub_v3_0.c243 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v3_0_init_cache_regs()
419 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); in mmhub_v3_0_gart_disable()
H A Dmmhub_v2_0.c286 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v2_0_init_cache_regs()
462 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); in mmhub_v2_0_gart_disable()
H A Dmmhub_v1_0.c166 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v1_0_init_cache_regs()
364 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in mmhub_v1_0_gart_disable()
H A Dgfxhub_v1_2.c229 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v1_2_xcc_init_cache_regs()
456 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v1_2_xcc_gart_disable()
H A Dmmhub_v1_8.c228 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v1_8_init_cache_regs()
455 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, in mmhub_v1_8_gart_disable()
H A Dgfxhub_v2_1.c218 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v2_1_init_cache_regs()
404 WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v2_1_gart_disable()
H A Dgmc_v7_0.c628 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in gmc_v7_0_gart_enable()
746 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in gmc_v7_0_gart_disable()
H A Dmmhub_v1_7.c184 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v1_7_init_cache_regs()
372 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in mmhub_v1_7_gart_disable()
H A Dgmc_v8_0.c843 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in gmc_v8_0_gart_enable()
978 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in gmc_v8_0_gart_disable()
H A Dmmhub_v9_4.c209 ENABLE_L2_CACHE, 1); in mmhub_v9_4_init_cache_regs()
436 ENABLE_L2_CACHE, 0); in mmhub_v9_4_gart_disable()
H A Dsid.h371 #define ENABLE_L2_CACHE (1 << 0) macro
/openbmc/linux/drivers/gpu/drm/radeon/
H A Drv770.c907 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in rv770_pcie_gart_enable()
984 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in rv770_agp_enable()
H A Drv770d.h643 #define ENABLE_L2_CACHE (1 << 0) macro
H A Dnid.h105 #define ENABLE_L2_CACHE (1 << 0) macro
H A Dsid.h370 #define ENABLE_L2_CACHE (1 << 0) macro
H A Dcikd.h488 #define ENABLE_L2_CACHE (1 << 0) macro
H A Devergreend.h1151 #define ENABLE_L2_CACHE (1 << 0) macro
H A Dr600d.h588 #define ENABLE_L2_CACHE (1 << 0) macro

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