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Searched refs:EA (Results 1 – 25 of 46) sorted by relevance

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/openbmc/qemu/target/hexagon/mmvec/
H A Dmacros.h108 #define fV_AL_CHECK(EA, MASK) \ argument
109 if ((EA) & (MASK)) { \
110 warn("aligning misaligned vector. EA=%08x", (EA)); \
123 #define fVLOG_VTCM_WORD_INCREMENT(EA, OFFSET, INC, IDX, ALIGNMENT, LEN) \ argument
126 target_ulong va = EA; \
127 target_ulong va_high = EA + LEN; \
134 #define fVLOG_VTCM_HALFWORD_INCREMENT(EA, OFFSET, INC, IDX, ALIGNMENT, LEN) \ argument
137 target_ulong va = EA; \
138 target_ulong va_high = EA + LEN; \
146 #define fVLOG_VTCM_HALFWORD_INCREMENT_DV(EA, OFFSET, INC, IDX, IDX2, IDX_H, \ argument
[all …]
/openbmc/qemu/target/hexagon/imported/
H A Dldst.idef34 …=memub","Load Unsigned Byte",ATTRIBS(A_MEMSIZE_1B,A_LOAD,A_REGWRSIZE_1B),"0",fLOAD(1,1,u,EA,RdV),0)
35 …DES(loadrb, "Rd32=memb", "Load signed Byte",ATTRIBS(A_MEMSIZE_1B,A_LOAD),"0",fLOAD(1,1,s,EA,RdV),0)
36 …"Load unsigned Half integer",ATTRIBS(A_REGWRSIZE_2B,A_MEMSIZE_2B,A_LOAD),"1",fLOAD(1,2,u,EA,RdV),1)
37 …, "Load signed Half integer",ATTRIBS(A_REGWRSIZE_2B,A_MEMSIZE_2B,A_LOAD),"1",fLOAD(1,2,s,EA,RdV),1)
38 …ri, "Rd32=memw", "Load Word",ATTRIBS(A_REGWRSIZE_4B,A_MEMSIZE_4B,A_LOAD),"2",fLOAD(1,4,u,EA,RdV),2)
39 …memd","Load Double integer",ATTRIBS(A_REGWRSIZE_8B,A_MEMSIZE_8B,A_LOAD),"3",fLOAD(1,8,u,EA,RddV),3)
45 fLOAD(1,2,u,EA,tmpV);
54 fLOAD(1,4,u,EA,tmpV);
66 fLOAD(1,2,u,EA,tmpV);
75 fLOAD(1,4,u,EA,tmpV);
[all …]
H A Dsubinsns.idef65 …A_REGWRSIZE_4B,A_MEMSIZE_4B,A_LOAD,A_SUBINSN),"load word", {fEA_RI(RsV,uiV); fLOAD(1,4,u,EA,RdV);})
66 …A_MEMSIZE_1B,A_LOAD,A_SUBINSN,A_REGWRSIZE_1B),"load byte", {fEA_RI(RsV,uiV); fLOAD(1,1,u,EA,RdV);})
68 …A_REGWRSIZE_2B,A_MEMSIZE_2B,A_LOAD,A_SUBINSN),"load half", {fEA_RI(RsV,uiV); fLOAD(1,2,s,EA,RdV);})
69 …A_REGWRSIZE_2B,A_MEMSIZE_2B,A_LOAD,A_SUBINSN),"load half", {fEA_RI(RsV,uiV); fLOAD(1,2,u,EA,RdV);})
70 …3:0)", ATTRIBS(A_MEMSIZE_1B,A_LOAD,A_SUBINSN),"load byte", {fEA_RI(RsV,uiV); fLOAD(1,1,s,EA,RdV);})
71 …SIZE_4B,A_MEMSIZE_4B,A_LOAD,A_SUBINSN),"load word", {fEA_RI(fREAD_SP(),uiV); fLOAD(1,4,u,EA,RdV);})
72 …IZE_8B,A_MEMSIZE_8B,A_LOAD,A_SUBINSN),"load dword",{fEA_RI(fREAD_SP(),uiV); fLOAD(1,8,u,EA,RddV);})
76 fLOAD(1,8,u,EA,tmp);
80 fWRITE_SP(EA+8); })
84 fLOAD(1,8,u,EA,tmp);
[all …]
H A Dsystem.idef36 …)",ATTRIBS(A_ICOP,A_ICFLUSHOP),"Instruction Cache Invalidate Address",{fEA_REG(RsV); fICINVA(EA);})
43 …",ATTRIBS(A_RESTRICT_PREFERSLOT0,A_DCFETCH),"Data Cache Prefetch",{fEA_RI(RsV,uiV); fDCFETCH(EA);})
46 …,A_RESTRICT_SLOT0ONLY,A_DCZEROA),"Zero an aligned 32-byte cacheline",{fEA_REG(RsV); fDCZEROA(EA);})
47 …TTRIBS(A_RESTRICT_SLOT0ONLY,A_DCFLUSHOP),"Data Cache Clean Address",{fEA_REG(RsV); fDCCLEANA(EA);})
48 …SLOT0ONLY,A_DCFLUSHOP),"Data Cache Clean and Invalidate Address",{fEA_REG(RsV); fDCCLEANINVA(EA);})
49 …_RESTRICT_SLOT0ONLY,A_DCFLUSHOP),"Data Cache Invalidate Address",{fEA_REG(RsV); fDCCLEANINVA(EA);})
H A Dmacros.def38 {mem_general_load_cancelled(thread,EA,insn);CANCEL;} , /* behavior */
44 {mem_general_store_cancelled(thread,EA,insn);CANCEL;} , /* behavior */
869 fEA_RI, /* Calculate EA with Register + Immediate Offset */
870 do { EA=REG+IMM; fDOCHKPAGECROSS(REG,EA); } while (0),
875 fEA_RRs, /* Calculate EA with Register + Registers scaled Offset */
876 do { EA=REG+(REG2<<SCALE); fDOCHKPAGECROSS(REG,EA); } while (0),
881 fEA_IRs, /* Calculate EA with Immediate + Registers scaled Offset */
882 do { EA=IMM+(REG<<SCALE); fDOCHKPAGECROSS(IMM,EA); } while (0),
887 fEA_IMM, /* Calculate EA with Immediate */
888 EA=IMM,
[all …]
/openbmc/qemu/target/hexagon/imported/mmvec/
H A Dmacros.def203 if ((EA) & (MASK)) {
204 warn("aligning misaligned vector. PC=%08x EA=%08x",thread->Regs[REG_PC],(EA));
351 GATHER_FUNCTION(EA,OFFSET,IDX, LEN, 4, IDX, 1);
357 GATHER_FUNCTION(EA,OFFSET,IDX, LEN, 2, IDX, 1);
363 GATHER_FUNCTION(EA,OFFSET,IDX, LEN, 2, (2*IDX2+IDX_H), 1);
369 GATHER_FUNCTION(EA,OFFSET,IDX, LEN, 4, IDX, fGETQBIT(QsV,4*IDX+i0));
375 GATHER_FUNCTION(EA,OFFSET,IDX, LEN, 2, IDX, fGETQBIT(QsV,2*IDX+i0));
382 GATHER_FUNCTION(EA,OFFSET,IDX, LEN, 2, (2*IDX2+IDX_H), fGETQBIT(QsV,2*IDX+i0));
454 SCATTER_FUNCTION (EA,OFFSET,IDX, LEN, 2, IDX, 1, IN);
460 SCATTER_FUNCTION (EA,OFFSET,IDX, LEN, 4, IDX, 1, IN);
[all …]
H A Dext.idef258 #define MMVEC_LD(TAG,DESCR,ATTRIB,NT) MMVEC_EACH_EA(TAG,DESCR,ATTRIB,NT,"Vd32=vmem","",fLOADMMV(EA,…
259 …C(TAG,DESCR,ATTRIB,NT) MMVEC_EACH_EA(TAG##_cur,DESCR,ATTRIB,NT,"Vd32.cur=vmem","",fLOADMMV(EA,VdV))
260 …T(TAG,DESCR,ATTRIB,NT) MMVEC_EACH_EA(TAG##_tmp,DESCR,ATTRIB,NT,"Vd32.tmp=vmem","",fLOADMMV(EA,VdV))
261 …MMVEC_LDU(TAG,DESCR,ATTRIB,NT) MMVEC_EACH_EA(TAG,DESCR,ATTRIB,NT,"Vd32=vmemu","",fLOADMMVU(EA,VdV))
265 MMVEC_EACH_EA(TAG##_qpred,DESCR,ATTRIB,NT,"if (Qv4) vmem","=Vs32",fSTOREMMVQ(EA,VsV,QvV)) \
266 MMVEC_EACH_EA(TAG##_nqpred,DESCR,ATTRIB,NT,"if (!Qv4) vmem","=Vs32",fSTOREMMVNQ(EA,VsV,QvV))
280 …itional Aligned Vector Load",ATTRIBS(ATTR_VMEM,A_LOAD,A_CVI_VA),,"Vd32=vmem",,Pv,fLOADMMV(EA,VdV);)
281 …ctor Load Cur",ATTRIBS(ATTR_VMEM,A_LOAD,A_CVI_VA,A_CVI_NEW),,"Vd32.cur=vmem",,Pv,fLOADMMV(EA,VdV);)
282 …ligned Vector Load Tmp",ATTRIBS(ATTR_VMEM,A_LOAD,A_CVI_TMP),,"Vd32.tmp=vmem",,Pv,fLOADMMV(EA,VdV);)
284 … Store",ATTRIBS(ATTR_VMEM,A_STORE,A_RESTRICT_SLOT0ONLY,A_CVI_VA),,"vmem","=Vs32",fSTOREMMV(EA,VsV))
[all …]
/openbmc/qemu/target/ppc/translate/
H A Dfp-impl.c.inc739 TCGv EA;
747 EA = tcg_temp_new();
749 gen_addr_reg_index(ctx, EA);
750 tcg_gen_qemu_ld_i64(t0, EA, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UQ));
757 TCGv EA;
764 EA = tcg_temp_new();
765 gen_addr_imm_index(ctx, EA, 0);
772 gen_qemu_ld64_i64(ctx, t0, EA);
774 tcg_gen_addi_tl(EA, EA, 8);
775 gen_qemu_ld64_i64(ctx, t0, EA);
[all …]
H A Dvsx-impl.c.inc40 TCGv EA;
45 EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]);
46 op(ctx, t0, EA);
61 TCGv EA;
69 EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]);
70 gen_qemu_ld64_i64(ctx, t0, EA);
72 tcg_gen_addi_tl(EA, EA, 8);
73 gen_qemu_ld64_i64(ctx, t0, EA);
80 TCGv EA;
89 EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]);
[all …]
H A Dvmx-impl.c.inc39 TCGv EA;
45 EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]);
46 tcg_gen_andi_tl(EA, EA, ~0xf);
47 tcg_gen_qemu_ld_i128(avr, EA, ctx->mem_idx,
62 TCGv EA;
68 EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]);
69 tcg_gen_andi_tl(EA, EA, ~0xf);
71 tcg_gen_qemu_st_i128(avr, EA, ctx->mem_idx,
86 TCGv EA;
91 EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]);
[all …]
/openbmc/qemu/target/hexagon/
H A Dmacros.h97 probe_noshuf_load(EA, SIZE, ctx->mem_idx); \
190 #define LOAD_CANCEL(EA) do { CANCEL; } while (0) argument
192 #define STORE_CANCEL(EA) { env->slot_cancelled |= (1 << slot); } argument
426 #define fEA_RI(REG, IMM) tcg_gen_addi_tl(EA, REG, IMM)
431 tcg_gen_add_tl(EA, REG, tmp); \
435 tcg_gen_shli_tl(EA, REG, SCALE); \
436 tcg_gen_addi_tl(EA, EA, IMM); \
441 EA = REG + IMM; \
445 EA = REG + (REG2 << SCALE); \
449 EA = IMM + (REG << SCALE); \
[all …]
H A Dgen_tcg.h59 gen_helper_fbrev(EA, RxV); \
70 tcg_gen_mov_tl(EA, RxV); \
76 tcg_gen_mov_tl(EA, RxV); \
86 fLOAD(1, SIZE, SIGN, EA, RES); \
113 tcg_gen_mov_tl(EA, RxV); \
120 fGEN_TCG_LOAD_pcr(0, fLOAD(1, 1, u, EA, RdV))
122 fGEN_TCG_LOAD_pcr(0, fLOAD(1, 1, s, EA, RdV))
124 fGEN_TCG_LOAD_pcr(1, fLOAD(1, 2, u, EA, RdV))
126 fGEN_TCG_LOAD_pcr(1, fLOAD(1, 2, s, EA, RdV))
128 fGEN_TCG_LOAD_pcr(2, fLOAD(1, 4, u, EA, RdV))
[all …]
H A Dgenptr.c762 static void gen_load_frame(DisasContext *ctx, TCGv_i64 frame, TCGv EA) in gen_load_frame() argument
765 CHECK_NOSHUF(EA, 8); in gen_load_frame()
766 tcg_gen_qemu_ld_i64(frame, EA, ctx->mem_idx, MO_TEUQ); in gen_load_frame()
771 static void gen_framecheck(TCGv EA, int framesize) in gen_framecheck() argument
1246 static void gen_vreg_store(DisasContext *ctx, TCGv EA, intptr_t srcoff, in gen_vreg_store() argument
1254 gen_helper_gather_store(tcg_env, EA, sl); in gen_vreg_store()
1260 tcg_gen_andi_tl(hex_vstore_addr[slot], EA, in gen_vreg_store()
1263 tcg_gen_mov_tl(hex_vstore_addr[slot], EA); in gen_vreg_store()
1273 static void gen_vreg_masked_store(DisasContext *ctx, TCGv EA, intptr_t srcoff, in gen_vreg_masked_store() argument
1280 tcg_gen_andi_tl(hex_vstore_addr[slot], EA, in gen_vreg_masked_store()
H A Dgen_tcg_hvx.h583 gen_vreg_load(ctx, DSTOFF, EA, true); \
711 gen_vreg_store(ctx, EA, OsN_off, insn->slot, true); \
748 gen_vreg_store(ctx, EA, SRCOFF, insn->slot, ALIGN); \
/openbmc/qemu/target/hexagon/idef-parser/
H A Dmacros.h.inc107 #define fEA_RI(REG, IMM) (EA = REG + IMM)
108 #define fEA_RRs(REG, REG2, SCALE) (EA = REG + (REG2 << SCALE))
109 #define fEA_IRs(IMM, REG, SCALE) (EA = IMM + (REG << SCALE))
110 #define fEA_IMM(IMM) (EA = IMM)
111 #define fEA_REG(REG) (EA = REG)
112 #define fEA_BREVR(REG) (EA = fbrev(REG))
113 #define fEA_GPI(IMM) (EA = fREAD_GP() + IMM)
H A Didef-parser.lex314 "LOAD_CANCEL(EA)" { return LOAD_CANCEL; }
315 "STORE_CANCEL(EA)" { return STORE_CANCEL; }
/openbmc/qemu/target/ppc/
H A Dtranslate.c2476 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, in gen_addr_imm_index() argument
2486 tcg_gen_movi_tl(EA, simm); in gen_addr_imm_index()
2488 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); in gen_addr_imm_index()
2490 tcg_gen_ext32u_tl(EA, EA); in gen_addr_imm_index()
2494 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); in gen_addr_imm_index()
2496 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); in gen_addr_imm_index()
2501 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) in gen_addr_reg_index() argument
2505 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); in gen_addr_reg_index()
2507 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); in gen_addr_reg_index()
2510 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); in gen_addr_reg_index()
[all …]
/openbmc/linux/Documentation/filesystems/ext4/
H A Dinlinedata.rst12 “system.data” within the inode body (“ibody EA”). This of course
14 If the data size increases beyond i_block + ibody EA, a regular block
31 attribute in the inode body, the EA value is an array of
33 i_block and EA space are treated as separate dirent blocks; directory
H A Deainode.rst9 a regular file inode. This “EA inode” is linked only from the extended
16 and i_generation of the **one** owning inode (in cases where the EA
17 inode is not referenced by multiple inodes) to verify that the EA inode
/openbmc/linux/drivers/tty/
H A Dn_gsm.c368 #define EA 0x01 macro
510 return c & EA; in gsm_read_ea()
826 *dp++ = (addr << 2) | (ocr << 1) | EA; in gsm_send()
830 *dp++ = EA; /* Length of data = 0 */ in gsm_send()
1102 *--dp = (msg->len << 1) | EA; in __gsm_data_queue()
1111 *--dp = (msg->addr << 2) | CR | EA; in __gsm_data_queue()
1113 *--dp = (msg->addr << 2) | EA; in __gsm_data_queue()
1206 *dp++ = (gsm_encode_modem(dlci) << 1) | EA; in gsm_dlci_data_output()
1340 *dp++ = (gsm_encode_modem(dlci) << 1) | EA; in gsm_dlci_modem_output()
1343 *dp++ = (brk << 4) | 2 | EA; /* Length, Break, EA */ in gsm_dlci_modem_output()
[all …]
/openbmc/openbmc/meta-openembedded/meta-multimedia/recipes-multimedia/dvb-apps/files/dvb-scan-table/dvb-t/
H A Duk-Midhurst3 # <http://www.digitaluk.co.uk/coveragechecker/main/tradeexport/GU28�9EA/NA/0/>
/openbmc/linux/arch/powerpc/kernel/
H A Dtraps.c1226 unsigned long EA; in emulate_string_inst() local
1234 EA = (rA == 0) ? 0 : regs->gpr[rA]; in emulate_string_inst()
1239 EA += NB_RB; in emulate_string_inst()
1257 EA &= 0xFFFFFFFF; in emulate_string_inst()
1262 if (get_user(val, (u8 __user *)EA)) in emulate_string_inst()
1273 if (put_user(val, (u8 __user *)EA)) in emulate_string_inst()
1278 EA += 1; in emulate_string_inst()
/openbmc/linux/Documentation/arch/x86/
H A Dzero-page.rst38 1EA/001 ALL edd_mbr_sig_buf_entries Number of entries in edd_mbr_sig_buffer
/openbmc/u-boot/doc/
H A DREADME.uniphier456 This mode is the most handy because EA[24] is always supported by the save pin
457 mode of the system bus. On the other hand, EA[25] is not supported for some
458 newer SoCs. Even if it is, EA[25] is not connected on most of the boards.
/openbmc/u-boot/arch/arm/cpu/armv7/
H A Dnonsec_virt.S75 bic r5, r5, #0x4a @ clear IRQ, EA, nET bits

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