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Searched refs:DUAL_DUNIT_CFG_REG (Results 1 – 7 of 7) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_centralization.c85 DUAL_DUNIT_CFG_REG, cs_enable_reg_val, MASK_ALL_BITS)); in ddr3_tip_centralization()
89 DUAL_DUNIT_CFG_REG, (1 << 3), (1 << 3))); in ddr3_tip_centralization()
483 if_id, DUAL_DUNIT_CFG_REG, in ddr3_tip_centralization()
521 if_id, DUAL_DUNIT_CFG_REG, in ddr3_tip_special_rx()
526 if_id, DUAL_DUNIT_CFG_REG, in ddr3_tip_special_rx()
H A Dddr3_training_leveling.c66 DUAL_DUNIT_CFG_REG, cs_enable_reg_val, in ddr3_tip_dynamic_read_leveling()
71 DUAL_DUNIT_CFG_REG, (1 << 3), (1 << 3))); in ddr3_tip_dynamic_read_leveling()
295 DUAL_DUNIT_CFG_REG, cs_enable_reg_val[if_id], in ddr3_tip_dynamic_read_leveling()
440 DUAL_DUNIT_CFG_REG, &cs_enable_reg_val[if_id], in ddr3_tip_dynamic_per_bit_read_leveling()
445 DUAL_DUNIT_CFG_REG, (1 << 3), (1 << 3))); in ddr3_tip_dynamic_per_bit_read_leveling()
747 DUAL_DUNIT_CFG_REG, cs_enable_reg_val[if_id], in ddr3_tip_dynamic_per_bit_read_leveling()
841 DUAL_DUNIT_CFG_REG, cs_enable_reg_val, MASK_ALL_BITS)); in ddr3_tip_dynamic_write_leveling()
848 DUAL_DUNIT_CFG_REG, 0, (1 << 3))); in ddr3_tip_dynamic_write_leveling()
1143 DUAL_DUNIT_CFG_REG, cs_enable_reg_val[if_id], in ddr3_tip_dynamic_write_leveling()
H A Dddr3_training_pbs.c64 DUAL_DUNIT_CFG_REG, cs_enable_reg_val, MASK_ALL_BITS)); in ddr3_tip_pbs()
69 DUAL_DUNIT_CFG_REG, (1 << 3), (1 << 3))); in ddr3_tip_pbs()
871 DUAL_DUNIT_CFG_REG, cs_enable_reg_val[if_id], in ddr3_tip_pbs()
H A Dddr3_training_ip_engine.c380 DUAL_DUNIT_CFG_REG, 1 << 3, 1 << 3)); in ddr3_tip_ip_training()
389 DUAL_DUNIT_CFG_REG, 0, 1 << 3)); in ddr3_tip_ip_training()
718 (dev_num, ACCESS_TYPE_UNICAST, if_id, DUAL_DUNIT_CFG_REG, in ddr3_tip_read_training_result()
862 DUAL_DUNIT_CFG_REG, (1 << 3), (1 << 3))); in ddr3_tip_load_all_pattern_to_mem()
H A Dmv_ddr_regs.h343 #define DUAL_DUNIT_CFG_REG 0x16d8 macro
H A Dmv_ddr_plat.c368 reg = reg_read(DUAL_DUNIT_CFG_REG); in ddr3_tip_a38x_select_ddr_controller()
375 reg_write(DUAL_DUNIT_CFG_REG, reg); in ddr3_tip_a38x_select_ddr_controller()
H A Dddr3_training.c380 if_id, DUAL_DUNIT_CFG_REG, 0, in hws_ddr3_tip_init_controller()
1301 DUAL_DUNIT_CFG_REG, 0, 0x8)); in ddr3_tip_freq_set()
1575 DUAL_DUNIT_CFG_REG, in ddr3_tip_freq_set()
2578 if_id, DUAL_DUNIT_CFG_REG, 1 << 3, in ddr3_tip_enable_init_sequence()