Searched refs:DSI_28nm_PHY_PLL_SDM_CFG0_BYP (Results 1 – 2 of 2) sorted by relevance
277 #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP 0x00000040 macro
181 sdm_cfg0 = DSI_28nm_PHY_PLL_SDM_CFG0_BYP; in dsi_pll_28nm_clk_set_rate()259 if (sdm0 & DSI_28nm_PHY_PLL_SDM_CFG0_BYP) { in dsi_pll_28nm_clk_recalc_rate()