Searched refs:DRP (Results 1 – 6 of 6) sorted by relevance
56 tristate "Analogix ANX7411 Type-C DRP Port controller driver"61 Say Y or M here if your system has Analogix ANX7411 Type-C DRP Port81 tristate "TI HD3SS3220 Type-C DRP Port controller driver"85 Say Y or M here if your system has TI HD3SS3220 Type-C DRP Port
7 The XADC has a DRP interface for communication. Currently two different8 frontends for the DRP interface exist. One that is only available on the ZYNQ15 UltraScale+ FPGAs from Xilinx. The System Monitor provides a DRP interface for
218 msg_port_write(MEM_CTLR, DRP, drp); in prog_decode_before_jedec()1181 drp = msg_port_read(MEM_CTLR, DRP); in perform_jedec_init()2426 msg_port_write(MEM_CTLR, DRP, drp); in prog_dra_drb()2555 drp = msg_port_read(MEM_CTLR, DRP); in ecc_enable()2559 msg_port_write(MEM_CTLR, DRP, drp); in ecc_enable()
16 #define DRP 0x00 macro
24 * +---------------------+ SW6-3 set to DRP
14 for example "[host] device" when DRP port is in host mode.