Home
last modified time | relevance | path

Searched refs:DPLL_VGA_MODE_DIS (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_dpll.c816 dpll = DPLL_VGA_MODE_DIS; in i9xx_compute_dpll()
895 dpll = DPLL_VGA_MODE_DIS; in i8xx_compute_dpll()
1213 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; in vlv_compute_dpll()
1231 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; in chv_compute_dpll()
1603 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); in i9xx_enable_pll()
1952 DPLL_VGA_MODE_DIS) == 0); in chv_enable_pll()
2006 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; in vlv_disable_pll()
2023 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; in chv_disable_pll()
2053 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); in i9xx_disable_pll()
H A Dintel_display_power_well.c1199 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; in vlv_display_power_well_init()
H A Dintel_display.c7934 DPLL_VGA_MODE_DIS | in i830_enable_pipe()
7963 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); in i830_enable_pipe()
8013 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); in i830_disable_pipe()
/openbmc/linux/drivers/gpu/drm/gma500/
H A Dcdv_intel_display.c227 REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS); in cdv_dpll_set_clock_cdv()
665 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set()
722 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); in cdv_intel_crtc_mode_set()
H A Dpsb_intel_display.c158 dpll = DPLL_VGA_MODE_DIS; in psb_intel_crtc_mode_set()
H A Dpsb_intel_reg.h232 #define DPLL_VGA_MODE_DIS (1 << 28) macro
H A Doaktrail_crtc.c527 dpll |= DPLL_VGA_MODE_DIS; in oaktrail_crtc_mode_set()
/openbmc/linux/drivers/gpu/drm/i915/
H A Di915_reg.h1434 #define DPLL_VGA_MODE_DIS (1 << 28) macro