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Searched refs:DPLL (Results 1 – 22 of 22) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/clock/ti/
H A Ddpll.txt1 Binding for Texas Instruments DPLL clock.
6 register-mapped DPLL with usually two selectable input clocks
12 for the actual DPLL clock.
39 - reg : offsets for the register set for controlling the DPLL.
45 "ssc-deltam" - DPLL supports spread spectrum clocking (SSC), contains
47 "ssc-modfreq" - DPLL supports spread spectrum clocking (SSC), contains
54 - DPLL mode setting - defining any one or more of the following overrides
56 - ti,low-power-stop : DPLL supports low power stop mode, gating output
57 - ti,low-power-bypass : DPLL output matches rate of parent bypass clock
58 - ti,lock : DPLL locks in programmed rate
[all …]
H A Dapll.txt11 a subtype of a DPLL [2], although a simplified one at that.
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_dpll.c1603 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); in i9xx_enable_pll()
1604 intel_de_write(dev_priv, DPLL(pipe), dpll); in i9xx_enable_pll()
1607 intel_de_posting_read(dev_priv, DPLL(pipe)); in i9xx_enable_pll()
1619 intel_de_write(dev_priv, DPLL(pipe), dpll); in i9xx_enable_pll()
1624 intel_de_write(dev_priv, DPLL(pipe), dpll); in i9xx_enable_pll()
1625 intel_de_posting_read(dev_priv, DPLL(pipe)); in i9xx_enable_pll()
1755 intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll); in _vlv_enable_pll()
1756 intel_de_posting_read(dev_priv, DPLL(pipe)); in _vlv_enable_pll()
1759 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) in _vlv_enable_pll()
1775 intel_de_write(dev_priv, DPLL(pipe), in vlv_enable_pll()
[all …]
H A Dintel_dvo.c455 dpll[pipe] = intel_de_rmw(dev_priv, DPLL(pipe), 0, DPLL_DVO_2X_MODE); in intel_dvo_init_dev()
461 intel_de_write(dev_priv, DPLL(pipe), dpll[pipe]); in intel_dvo_init_dev()
H A Dintel_display_power_well.c1197 u32 val = intel_de_read(dev_priv, DPLL(pipe)); in vlv_display_power_well_init()
1203 intel_de_write(dev_priv, DPLL(pipe), val); in vlv_display_power_well_init()
1356 (intel_de_read(dev_priv, DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) in assert_chv_phy_status()
H A Dintel_display.c370 dpll_reg = DPLL(0); in vlv_wait_port_ready()
374 dpll_reg = DPLL(0); in vlv_wait_port_ready()
2972 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe)); in i9xx_get_pipe_config()
2983 DPLL(crtc->pipe)); in i9xx_get_pipe_config()
7963 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); in i830_enable_pipe()
7964 intel_de_write(dev_priv, DPLL(pipe), dpll); in i830_enable_pipe()
7967 intel_de_posting_read(dev_priv, DPLL(pipe)); in i830_enable_pipe()
7975 intel_de_write(dev_priv, DPLL(pipe), dpll); in i830_enable_pipe()
7979 intel_de_write(dev_priv, DPLL(pipe), dpll); in i830_enable_pipe()
7980 intel_de_posting_read(dev_priv, DPLL(pipe)); in i830_enable_pipe()
[all …]
H A Dintel_pps.c122 pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE; in vlv_power_sequencer_kick()
H A Dintel_display_power.c1779 u32 status = intel_de_read(dev_priv, DPLL(PIPE_A)); in chv_phy_control_init()
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Dclk.h19 #define DPLL 9 macro
/openbmc/linux/include/dt-bindings/clock/
H A Dxlnx-zynqmp-clk.h15 #define DPLL 3 macro
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3368.h16 DPLL, enumerator
/openbmc/linux/arch/arm/mach-omap2/
H A Dsleep24xx.S60 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
/openbmc/u-boot/board/rockchip/evb_rv1108/
H A DREADME37 APLL: 600000000 DPLL:792000000 GPLL:384000000
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos5422-odroid-core.dtsi101 /* derived from 600MHz DPLL */
203 /* derived from 600MHz DPLL */
239 /* derived from 600MHz DPLL */
251 /* derived from 600MHz DPLL */
266 /* derived from 600MHz DPLL */
/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3368.c147 dpll = rkclk_pll_get_rate(cru, DPLL); in rkclk_init()
305 rkclk_set_pll(cru, DPLL, dpll_cfg); in rk3368_ddr_set_clk()
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dti-phy.txt10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
/openbmc/linux/Documentation/arch/arm/omap/
H A Ddss.rst32 - Use DSI DPLL to create DSS FCK
301 Using DSI DPLL to generate pixel clock it is possible produce the pixel clock
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
H A Dreg.h256 #define DPLL 0x034A macro
/openbmc/u-boot/arch/arm/mach-exynos/
H A Dclock.c1049 const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL, IPLL, EPLL, in exynos5800_get_lcd_clk()
/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drk3036.dtsi235 * Fix the emac parent clock is DPLL instead of APLL.
/openbmc/linux/Documentation/networking/device_drivers/hamradio/
H A Dz8530drv.rst308 present at all (BayCom). It feeds back the output of the DPLL
/openbmc/linux/drivers/gpu/drm/i915/
H A Di915_reg.h1415 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) macro