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Searched refs:DPCD_TRAINING_LANE0_SET (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/drivers/video/
H A Dlogicore_dp_dpcd.h66 #define DPCD_TRAINING_LANE0_SET 0x00103 macro
H A Dlogicore_dp_tx.c1161 status = aux_write(dev, DPCD_TRAINING_LANE0_SET, 4, aux_data); in adj_vswing_preemp()
/openbmc/u-boot/drivers/video/exynos/
H A Dexynos_dp.c582 DPCD_TRAINING_LANE0_SET, 4, lt_ctl_val); in exynos_dp_process_clock_recovery()
681 DPCD_TRAINING_LANE0_SET, in exynos_dp_process_equalizer_training()
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dedp_rk3288.h468 #define DPCD_TRAINING_LANE0_SET (0x0103) macro
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Ddp.h623 #define DPCD_TRAINING_LANE0_SET (0x0103) macro
/openbmc/u-boot/drivers/video/rockchip/
H A Drk_edp.c482 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_LANE0_SET, in rk_edp_link_train_cr()