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Searched refs:DPCD_MAX_LANE_COUNT (Results 1 – 11 of 11) sorted by relevance

/openbmc/qemu/include/hw/display/
H A Ddpcd.h44 #define DPCD_MAX_LANE_COUNT 0x02 macro
/openbmc/linux/drivers/gpu/drm/i915/gvt/
H A Ddisplay.h81 #define DPCD_MAX_LANE_COUNT 0x002 macro
/openbmc/qemu/hw/display/
H A Ddpcd.c104 s->dpcd_info[DPCD_MAX_LANE_COUNT] = DPCD_FOUR_LANES; in dpcd_reset()
/openbmc/u-boot/drivers/video/
H A Dlogicore_dp_dpcd.h18 #define DPCD_MAX_LANE_COUNT 0x00002 macro
H A Dlogicore_dp_tx.c758 rx_max_lane_count = dp_tx->dpcd_rx_caps[DPCD_MAX_LANE_COUNT] & in get_rx_capabilities()
774 dp_tx->dpcd_rx_caps[DPCD_MAX_LANE_COUNT] & in get_rx_capabilities()
1512 if (dp_tx->dpcd_rx_caps[DPCD_MAX_LANE_COUNT] & DPCD_TPS3_SUPPORT_MASK) in training_state_channel_equalization()
/openbmc/u-boot/drivers/video/exynos/
H A Dexynos_dp.c217 temp = buf[DPCD_MAX_LANE_COUNT] & 0x1f; in exynos_dp_handle_edid()
218 if (buf[DPCD_MAX_LANE_COUNT] & 0x80) in exynos_dp_handle_edid()
223 temp = buf[DPCD_MAX_LANE_COUNT]; in exynos_dp_handle_edid()
/openbmc/linux/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_core.h26 #define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f) macro
H A Danx7625.h378 #define DPCD_MAX_LANE_COUNT 0x02 macro
H A Danalogix_dp_core.c638 *lane_count = DPCD_MAX_LANE_COUNT(data); in analogix_dp_get_max_rx_lane_count()
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dedp_rk3288.h453 #define DPCD_MAX_LANE_COUNT (0x0002) macro
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Ddp.h619 #define DPCD_MAX_LANE_COUNT (0x0002) macro