Searched refs:DMC (Results 1 – 15 of 15) sorted by relevance
6 PMUs such as the Level 3 Cache (L3C), DDR4 Memory Controller (DMC) and9 The DMC has 8 interleaved channels and the L3C has 16 interleaved tiles.13 The DMC and L3C support up to 4 counters, while the CCPI2 supports up to 816 overflow interrupt. DMC and L3C counters are 32-bit and read every 2 seconds.21 The thunderx2_pmu driver registers per-socket perf PMUs for the DMC and22 L3C devices. Each PMU can be used to count up to 4 (DMC/L3C) or up to 8
19 #define DMC 0x600000UL macro1978 #define RXDMA_CFIG1(IDX) (DMC + 0x00000UL + (IDX) * 0x200UL)1984 #define RXDMA_CFIG2(IDX) (DMC + 0x00008UL + (IDX) * 0x200UL)1990 #define RBR_CFIG_A(IDX) (DMC + 0x00010UL + (IDX) * 0x200UL)1996 #define RBR_CFIG_B(IDX) (DMC + 0x00018UL + (IDX) * 0x200UL)2026 #define RBR_KICK(IDX) (DMC + 0x00020UL + (IDX) * 0x200UL)2029 #define RBR_STAT(IDX) (DMC + 0x00028UL + (IDX) * 0x200UL)2032 #define RBR_HDH(IDX) (DMC + 0x00030UL + (IDX) * 0x200UL)2035 #define RBR_HDL(IDX) (DMC + 0x00038UL + (IDX) * 0x200UL)2038 #define RCRCFIG_A(IDX) (DMC + 0x00040UL + (IDX) * 0x200UL)[all …]
17 This adds driver for Samsung Exynos5422 SoC DMC (Dynamic Memory19 Frequency Scaling in DMC and DRAM. It also supports changing timings
6 Failed to load DMC firmware
16 DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
198 DMC Firmware Support202 :doc: DMC Firmware Support487 display microcontroller (DMC). The driver is responsible for loading the489 to WOPCM using the DMA engine, while the DMC firmware is written through MMIO.561 DMC section in Microcontrollers563 See `DMC Firmware Support`_
166 in the DDR4 Memory Controller (DMC).184 tristate "Enable PMU support for the ARM DMC-620 memory controller"187 Support for PMU events monitoring on the ARM DMC-620 memory
4 The RK3368 DMC (dynamic memory controller) driver supports setup/initialisation
133 tristate "ARM RK3399 DMC DEVFREQ Driver"140 This adds the DEVFREQ driver for the RK3399 DMC(Dynamic Memory Controller).
103 SEC_PD(DMC, GENPD_FLAG_ALWAYS_ON),
349 ldr r1, =0x8fefeeb @ DMC[1:0] PDMA0[3] IMEM[5]
539 tristate "ARM DMC-520 ECC"543 SoCs with ARM DMC-520 DRAM controller.
24 binary to perform a malicious action when executed [DMC-CBC-ATTACK]. Since440 [DMC-CBC-ATTACK] https://www.jakoblell.com/blog/2013/12/22/practical-malleability-attack-agains…
939 - DMC TSC-10/251018 bool "DMC TSC-10/25 device support" if EXPERT
6237 DMC FREQUENCY DRIVER FOR SAMSUNG EXYNOS5422