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Searched refs:DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK (Results 1 – 24 of 24) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsid.h2067 #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x20000 macro
H A Ddce_v6_0.c99 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
H A Ddce_v8_0.c94 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
H A Ddce_v10_0.c94 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
H A Ddce_v11_0.c98 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h5607 #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x00020000L macro
H A Ddce_8_0_sh_mask.h6909 #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x20000 macro
H A Ddce_10_0_sh_mask.h14906 #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x20000 macro
H A Ddce_11_0_sh_mask.h15054 #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x20000 macro
H A Ddce_11_2_sh_mask.h15716 #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x20000 macro
H A Ddce_12_0_sh_mask.h8002 #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_sh_mask.h493 #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK … macro
H A Ddcn_3_0_3_sh_mask.h2544 #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK … macro
H A Ddcn_3_0_1_sh_mask.h3909 #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK … macro
H A Ddcn_2_1_0_sh_mask.h3695 #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK … macro
H A Ddcn_3_2_1_sh_mask.h1193 #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK … macro
H A Ddcn_1_0_sh_mask.h4977 #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK … macro
H A Ddcn_3_1_2_sh_mask.h3667 #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK … macro
H A Ddcn_3_1_6_sh_mask.h4236 #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK … macro
H A Ddcn_3_0_2_sh_mask.h3876 #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK … macro
H A Ddcn_3_1_4_sh_mask.h12032 #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK … macro
H A Ddcn_3_0_0_sh_mask.h3980 #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK … macro
H A Ddcn_2_0_0_sh_mask.h3963 #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK … macro
H A Ddcn_3_2_0_sh_mask.h1195 #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK … macro