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Searched refs:DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK (Results 1 – 23 of 23) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsid.h2070 #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x20000 macro
H A Ddce_v6_0.c114 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
H A Ddce_v8_0.c109 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
H A Ddce_v10_0.c109 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
H A Ddce_v11_0.c113 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h5471 #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x00020000L macro
H A Ddce_8_0_sh_mask.h7075 #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x20000 macro
H A Ddce_10_0_sh_mask.h15070 #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x20000 macro
H A Ddce_11_0_sh_mask.h15218 #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x20000 macro
H A Ddce_11_2_sh_mask.h15880 #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x20000 macro
H A Ddce_12_0_sh_mask.h8166 #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h2660 #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK … macro
H A Ddcn_3_0_1_sh_mask.h4025 #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK … macro
H A Ddcn_2_1_0_sh_mask.h3828 #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK … macro
H A Ddcn_3_2_1_sh_mask.h1305 #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK … macro
H A Ddcn_1_0_sh_mask.h5109 #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK … macro
H A Ddcn_3_1_2_sh_mask.h3783 #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK … macro
H A Ddcn_3_1_6_sh_mask.h4352 #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK … macro
H A Ddcn_3_0_2_sh_mask.h3992 #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK … macro
H A Ddcn_3_1_4_sh_mask.h12149 #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK … macro
H A Ddcn_3_0_0_sh_mask.h4096 #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK … macro
H A Ddcn_2_0_0_sh_mask.h4096 #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK … macro
H A Ddcn_3_2_0_sh_mask.h1307 #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK … macro