Home
last modified time | relevance | path

Searched refs:DEBUG_WL_FULL_S (Results 1 – 1 of 1) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_write_leveling.c21 DEBUG_WL_FULL_S(s); DEBUG_WL_FULL_D(d, l); DEBUG_WL_FULL_S("\n")
36 #define DEBUG_WL_FULL_S(s) puts(s) macro
39 #define DEBUG_WL_FULL_S(s) macro
701 DEBUG_WL_FULL_S("DDR3 - Write Leveling - Qoff and RTT Values are set for all Cs\n"); in ddr3_write_leveling_sw()
709 DEBUG_WL_FULL_S("DDR3 - Write Leveling - SW Override Enabled\n"); in ddr3_write_leveling_sw()
726 DEBUG_WL_FULL_S("DDR3 - Write Leveling - Refresh X9\n"); in ddr3_write_leveling_sw()
744 DEBUG_WL_FULL_S("DDR3 - Write Leveling - Configure MR1 for current Cs: WL-on,OB-on\n"); in ddr3_write_leveling_sw()
867 DEBUG_WL_FULL_S("DDR3 - Write Leveling - Finished WL procedure for all Cs\n"); in ddr3_write_leveling_sw()
936 DEBUG_WL_FULL_S("DDR3 - Write Leveling - Qoff and RTT Values are set for all Cs\n"); in ddr3_write_leveling_sw_reg_dimm()
944 DEBUG_WL_FULL_S("DDR3 - Write Leveling - SW Override Enabled\n"); in ddr3_write_leveling_sw_reg_dimm()
[all …]