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Searched refs:DDR_TIMING_CFG_0 (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/include/configs/
H A Dls1021aiot.h31 #define DDR_TIMING_CFG_0 0x50550004 macro
H A Dls1021atwr.h32 #define DDR_TIMING_CFG_0 0x50550004 macro
/openbmc/u-boot/board/freescale/ls1021aiot/
H A Dls1021aiot.c56 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); in ddrmc_init()
/openbmc/u-boot/board/freescale/ls1021atwr/
H A Dls1021atwr.c148 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); in ddrmc_init()