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Searched refs:DDR_MODE_DDR3 (Results 1 – 7 of 7) sorted by relevance

/openbmc/u-boot/arch/arm/mach-exynos/
H A Ddmc_common.c79 if (mode == DDR_MODE_DDR3) { in update_reset_dll()
163 if (param->mem_type == DDR_MODE_DDR3) { in mem_ctrl_init()
H A Ddmc_init_ddr3.c77 update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3); in ddr3_mem_ctrl_init()
102 update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3); in ddr3_mem_ctrl_init()
211 update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3); in ddr3_mem_ctrl_init()
493 val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT); in ddr3_mem_ctrl_init()
498 val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT); in ddr3_mem_ctrl_init()
567 update_reset_dll(&drex0->phycontrol0, DDR_MODE_DDR3); in ddr3_mem_ctrl_init()
568 update_reset_dll(&drex1->phycontrol0, DDR_MODE_DDR3); in ddr3_mem_ctrl_init()
H A Dclock_init_exynos5.c140 .mem_type = DDR_MODE_DDR3,
266 .mem_type = DDR_MODE_DDR3,
369 .mem_type = DDR_MODE_DDR3,
/openbmc/u-boot/board/samsung/arndale/
H A Darndale_spl.c20 .mem_type = DDR_MODE_DDR3,
/openbmc/u-boot/board/samsung/smdk5250/
H A Dsmdk5250_spl.c22 .mem_type = DDR_MODE_DDR3,
/openbmc/u-boot/board/samsung/smdk5420/
H A Dsmdk5420_spl.c22 .mem_type = DDR_MODE_DDR3,
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Ddmc.h433 DDR_MODE_DDR3, enumerator