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Searched refs:DDRC_PCFGQOS1_0 (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/board/freescale/imx8mq_evk/
H A Dlpddr4_timing_b0.c125 { DDRC_PCFGQOS1_0(0), 0x0062ffff },
H A Dlpddr4_timing.c87 { DDRC_PCFGQOS1_0(0), 0x00620790 },
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h522 #define DDRC_PCFGQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x498) macro