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Searched refs:DDR2_CONF3_REG_VAL (Results 1 – 1 of 1) sorted by relevance

/openbmc/u-boot/arch/mips/mach-ath79/qca953x/
H A Dddr.c94 #define DDR2_CONF3_REG_VAL (DDR_TWR_MSB | DDR_TRFC_MSB(2)) macro
328 writel(DDR2_CONF3_REG_VAL, regs + QCA953X_DDR_REG_CONFIG3); in ddr_init()