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Searched refs:DDR1 (Results 1 – 7 of 7) sorted by relevance

/openbmc/u-boot/doc/SPL/
H A DREADME.omap333 DDR1: 0x80000000 - 0xBFFFFFFF
49 For the areas that reside within DDR1 they must not be used prior to s_init()
/openbmc/u-boot/board/freescale/s32v234evb/
H A Ds32v234evb.c23 lpddr2_config_iomux(DDR1); in setup_iomux_ddr()
H A Dlpddr2.c41 case DDR1: in lpddr2_config_iomux()
/openbmc/u-boot/arch/arm/include/asm/arch-s32v234/
H A Dddr.h10 #define DDR1 1 macro
/openbmc/u-boot/drivers/ddr/fsl/
H A DKconfig143 bool "Freescale DDR1 controller"
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dti-aemif.txt7 per chip select. Synchronous memories such as DDR1 SD RAM, SDR SDRAM
/openbmc/u-boot/
H A DREADME432 Freescale DDR1 controller.
447 Board config to use DDR1. It can be enabled for SoCs with
448 Freescale DDR1 or DDR2 controllers, depending on the board