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Searched refs:DC_WR_CH_CONF (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/drivers/gpu/ipu-v3/
H A Dipu-dc.c44 #define DC_WR_CH_CONF 0x0 macro
217 reg = readl(dc->base + DC_WR_CH_CONF); in ipu_dc_init_sync()
222 writel(reg, dc->base + DC_WR_CH_CONF); in ipu_dc_init_sync()
250 reg = readl(dc->base + DC_WR_CH_CONF); in ipu_dc_enable_channel()
252 writel(reg, dc->base + DC_WR_CH_CONF); in ipu_dc_enable_channel()
260 val = readl(dc->base + DC_WR_CH_CONF); in ipu_dc_disable_channel()
262 writel(val, dc->base + DC_WR_CH_CONF); in ipu_dc_disable_channel()
373 priv->channels[1].base + DC_WR_CH_CONF); in ipu_dc_init()
375 priv->channels[5].base + DC_WR_CH_CONF); in ipu_dc_init()
/openbmc/u-boot/drivers/video/
H A Dipu_disp.c572 __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); in ipu_dc_init()
633 reg = __raw_readl(DC_WR_CH_CONF(6 - dc_chan)); in ipu_dp_dc_enable()
637 __raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan)); in ipu_dp_dc_enable()
640 reg = __raw_readl(DC_WR_CH_CONF(dc_chan)); in ipu_dp_dc_enable()
642 __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); in ipu_dp_dc_enable()
709 reg = __raw_readl(DC_WR_CH_CONF(dc_chan)); in ipu_dp_dc_disable()
710 __raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan)); in ipu_dp_dc_disable()
713 __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); in ipu_dp_dc_disable()
721 reg = __raw_readl(DC_WR_CH_CONF(dc_chan)); in ipu_dp_dc_disable()
723 __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); in ipu_dp_dc_disable()
H A Dipu_regs.h386 #define DC_WR_CH_CONF(ch) (&dc_ch_offset(ch)->wr_ch_conf) macro
389 #define DC_WR_CH_CONF_1 DC_WR_CH_CONF(1)
390 #define DC_WR_CH_CONF_5 DC_WR_CH_CONF(5)