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Searched refs:DCLK_VOP0_DIV (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-pinephone-pro.dts599 assigned-clocks = <&cru DCLK_VOP0_DIV>, <&cru DCLK_VOP0>,
602 assigned-clock-parents = <&cru PLL_GPLL>, <&cru DCLK_VOP0_DIV>;
/openbmc/u-boot/include/dt-bindings/clock/
H A Drk3399-cru.h131 #define DCLK_VOP0_DIV 182 macro
/openbmc/linux/include/dt-bindings/clock/
H A Drk3399-cru.h131 #define DCLK_VOP0_DIV 182 macro
/openbmc/linux/drivers/clk/rockchip/
H A Dclk-rk3399.c1165 COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, 0,