xref: /openbmc/linux/drivers/dma/ste_dma40_ll.h (revision 75bf465f0bc33e9b776a46d6a1b9b990f5fb7c37)
1  /* SPDX-License-Identifier: GPL-2.0-only */
2  /*
3   * Copyright (C) ST-Ericsson SA 2007-2010
4   * Author: Per Friden <per.friden@stericsson.com> for ST-Ericsson SA
5   * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson SA
6   */
7  #ifndef STE_DMA40_LL_H
8  #define STE_DMA40_LL_H
9  
10  #define D40_DREG_PCBASE		0x400
11  #define D40_DREG_PCDELTA	(8 * 4)
12  #define D40_LLI_ALIGN		16 /* LLI alignment must be 16 bytes. */
13  
14  #define D40_LCPA_CHAN_SIZE 32
15  #define D40_LCPA_CHAN_DST_DELTA 16
16  
17  #define D40_TYPE_TO_GROUP(type) (type / 16)
18  #define D40_TYPE_TO_EVENT(type) (type % 16)
19  #define D40_GROUP_SIZE 8
20  #define D40_PHYS_TO_GROUP(phys) ((phys & (D40_GROUP_SIZE - 1)) / 2)
21  
22  /* Most bits of the CFG register are the same in log as in phy mode */
23  #define D40_SREG_CFG_MST_POS		15
24  #define D40_SREG_CFG_TIM_POS		14
25  #define D40_SREG_CFG_EIM_POS		13
26  #define D40_SREG_CFG_LOG_INCR_POS	12
27  #define D40_SREG_CFG_PHY_PEN_POS	12
28  #define D40_SREG_CFG_PSIZE_POS		10
29  #define D40_SREG_CFG_ESIZE_POS		 8
30  #define D40_SREG_CFG_PRI_POS		 7
31  #define D40_SREG_CFG_LBE_POS		 6
32  #define D40_SREG_CFG_LOG_GIM_POS	 5
33  #define D40_SREG_CFG_LOG_MFU_POS	 4
34  #define D40_SREG_CFG_PHY_TM_POS		 4
35  #define D40_SREG_CFG_PHY_EVTL_POS	 0
36  
37  
38  /* Standard channel parameters - basic mode (element register) */
39  #define D40_SREG_ELEM_PHY_ECNT_POS	16
40  #define D40_SREG_ELEM_PHY_EIDX_POS	 0
41  
42  #define D40_SREG_ELEM_PHY_ECNT_MASK	(0xFFFF << D40_SREG_ELEM_PHY_ECNT_POS)
43  
44  /* Standard channel parameters - basic mode (Link register) */
45  #define D40_SREG_LNK_PHY_TCP_POS	0
46  #define D40_SREG_LNK_PHY_LMP_POS	1
47  #define D40_SREG_LNK_PHY_PRE_POS	2
48  /*
49   * Source  destination link address. Contains the
50   * 29-bit byte word aligned address of the reload area.
51   */
52  #define D40_SREG_LNK_PHYS_LNK_MASK	0xFFFFFFF8UL
53  
54  /* Standard basic channel logical mode */
55  
56  /* Element register */
57  #define D40_SREG_ELEM_LOG_ECNT_POS	16
58  #define D40_SREG_ELEM_LOG_LIDX_POS	 8
59  #define D40_SREG_ELEM_LOG_LOS_POS	 1
60  #define D40_SREG_ELEM_LOG_TCP_POS	 0
61  
62  #define D40_SREG_ELEM_LOG_LIDX_MASK	(0xFF << D40_SREG_ELEM_LOG_LIDX_POS)
63  
64  /* Link register */
65  #define D40_EVENTLINE_POS(i)		(2 * i)
66  #define D40_EVENTLINE_MASK(i)		(0x3 << D40_EVENTLINE_POS(i))
67  
68  /* Standard basic channel logical params in memory */
69  
70  /* LCSP0 */
71  #define D40_MEM_LCSP0_ECNT_POS		16
72  #define D40_MEM_LCSP0_SPTR_POS		 0
73  
74  #define D40_MEM_LCSP0_ECNT_MASK		(0xFFFF << D40_MEM_LCSP0_ECNT_POS)
75  #define D40_MEM_LCSP0_SPTR_MASK		(0xFFFF << D40_MEM_LCSP0_SPTR_POS)
76  
77  /* LCSP1 */
78  #define D40_MEM_LCSP1_SPTR_POS		16
79  #define D40_MEM_LCSP1_SCFG_MST_POS	15
80  #define D40_MEM_LCSP1_SCFG_TIM_POS	14
81  #define D40_MEM_LCSP1_SCFG_EIM_POS	13
82  #define D40_MEM_LCSP1_SCFG_INCR_POS	12
83  #define D40_MEM_LCSP1_SCFG_PSIZE_POS	10
84  #define D40_MEM_LCSP1_SCFG_ESIZE_POS	 8
85  #define D40_MEM_LCSP1_SLOS_POS		 1
86  #define D40_MEM_LCSP1_STCP_POS		 0
87  
88  #define D40_MEM_LCSP1_SPTR_MASK		(0xFFFF << D40_MEM_LCSP1_SPTR_POS)
89  #define D40_MEM_LCSP1_SCFG_TIM_MASK	(0x1 << D40_MEM_LCSP1_SCFG_TIM_POS)
90  #define D40_MEM_LCSP1_SCFG_INCR_MASK	(0x1 << D40_MEM_LCSP1_SCFG_INCR_POS)
91  #define D40_MEM_LCSP1_SCFG_PSIZE_MASK	(0x3 << D40_MEM_LCSP1_SCFG_PSIZE_POS)
92  #define D40_MEM_LCSP1_SLOS_MASK		(0x7F << D40_MEM_LCSP1_SLOS_POS)
93  #define D40_MEM_LCSP1_STCP_MASK		(0x1 << D40_MEM_LCSP1_STCP_POS)
94  
95  /* LCSP2 */
96  #define D40_MEM_LCSP2_ECNT_POS		16
97  
98  #define D40_MEM_LCSP2_ECNT_MASK		(0xFFFF << D40_MEM_LCSP2_ECNT_POS)
99  
100  /* LCSP3 */
101  #define D40_MEM_LCSP3_DCFG_MST_POS	15
102  #define D40_MEM_LCSP3_DCFG_TIM_POS	14
103  #define D40_MEM_LCSP3_DCFG_EIM_POS	13
104  #define D40_MEM_LCSP3_DCFG_INCR_POS	12
105  #define D40_MEM_LCSP3_DCFG_PSIZE_POS	10
106  #define D40_MEM_LCSP3_DCFG_ESIZE_POS	 8
107  #define D40_MEM_LCSP3_DLOS_POS		 1
108  #define D40_MEM_LCSP3_DTCP_POS		 0
109  
110  #define D40_MEM_LCSP3_DLOS_MASK		(0x7F << D40_MEM_LCSP3_DLOS_POS)
111  #define D40_MEM_LCSP3_DTCP_MASK		(0x1 << D40_MEM_LCSP3_DTCP_POS)
112  
113  
114  /* Standard channel parameter register offsets */
115  #define D40_CHAN_REG_SSCFG	0x00
116  #define D40_CHAN_REG_SSELT	0x04
117  #define D40_CHAN_REG_SSPTR	0x08
118  #define D40_CHAN_REG_SSLNK	0x0C
119  #define D40_CHAN_REG_SDCFG	0x10
120  #define D40_CHAN_REG_SDELT	0x14
121  #define D40_CHAN_REG_SDPTR	0x18
122  #define D40_CHAN_REG_SDLNK	0x1C
123  
124  /* DMA Register Offsets */
125  #define D40_DREG_GCC		0x000
126  #define D40_DREG_GCC_ENA	0x1
127  /* This assumes that there are only 4 event groups */
128  #define D40_DREG_GCC_ENABLE_ALL	0x3ff01
129  #define D40_DREG_GCC_EVTGRP_POS 8
130  #define D40_DREG_GCC_SRC 0
131  #define D40_DREG_GCC_DST 1
132  #define D40_DREG_GCC_EVTGRP_ENA(x, y) \
133  	(1 << (D40_DREG_GCC_EVTGRP_POS + 2 * x + y))
134  
135  #define D40_DREG_PRTYP		0x004
136  #define D40_DREG_PRSME		0x008
137  #define D40_DREG_PRSMO		0x00C
138  #define D40_DREG_PRMSE		0x010
139  #define D40_DREG_PRMSO		0x014
140  #define D40_DREG_PRMOE		0x018
141  #define D40_DREG_PRMOO		0x01C
142  #define D40_DREG_PRMO_PCHAN_BASIC		0x1
143  #define D40_DREG_PRMO_PCHAN_MODULO		0x2
144  #define D40_DREG_PRMO_PCHAN_DOUBLE_DST		0x3
145  #define D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG	0x1
146  #define D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY	0x2
147  #define D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG	0x3
148  
149  #define D40_DREG_LCPA		0x020
150  #define D40_DREG_LCLA		0x024
151  
152  #define D40_DREG_SSEG1		0x030
153  #define D40_DREG_SSEG2		0x034
154  #define D40_DREG_SSEG3		0x038
155  #define D40_DREG_SSEG4		0x03C
156  
157  #define D40_DREG_SCEG1		0x040
158  #define D40_DREG_SCEG2		0x044
159  #define D40_DREG_SCEG3		0x048
160  #define D40_DREG_SCEG4		0x04C
161  
162  #define D40_DREG_ACTIVE		0x050
163  #define D40_DREG_ACTIVO		0x054
164  #define D40_DREG_CIDMOD		0x058
165  #define D40_DREG_TCIDV		0x05C
166  #define D40_DREG_PCMIS		0x060
167  #define D40_DREG_PCICR		0x064
168  #define D40_DREG_PCTIS		0x068
169  #define D40_DREG_PCEIS		0x06C
170  
171  #define D40_DREG_SPCMIS		0x070
172  #define D40_DREG_SPCICR		0x074
173  #define D40_DREG_SPCTIS		0x078
174  #define D40_DREG_SPCEIS		0x07C
175  
176  #define D40_DREG_LCMIS0		0x080
177  #define D40_DREG_LCMIS1		0x084
178  #define D40_DREG_LCMIS2		0x088
179  #define D40_DREG_LCMIS3		0x08C
180  #define D40_DREG_LCICR0		0x090
181  #define D40_DREG_LCICR1		0x094
182  #define D40_DREG_LCICR2		0x098
183  #define D40_DREG_LCICR3		0x09C
184  #define D40_DREG_LCTIS0		0x0A0
185  #define D40_DREG_LCTIS1		0x0A4
186  #define D40_DREG_LCTIS2		0x0A8
187  #define D40_DREG_LCTIS3		0x0AC
188  #define D40_DREG_LCEIS0		0x0B0
189  #define D40_DREG_LCEIS1		0x0B4
190  #define D40_DREG_LCEIS2		0x0B8
191  #define D40_DREG_LCEIS3		0x0BC
192  
193  #define D40_DREG_SLCMIS1	0x0C0
194  #define D40_DREG_SLCMIS2	0x0C4
195  #define D40_DREG_SLCMIS3	0x0C8
196  #define D40_DREG_SLCMIS4	0x0CC
197  
198  #define D40_DREG_SLCICR1	0x0D0
199  #define D40_DREG_SLCICR2	0x0D4
200  #define D40_DREG_SLCICR3	0x0D8
201  #define D40_DREG_SLCICR4	0x0DC
202  
203  #define D40_DREG_SLCTIS1	0x0E0
204  #define D40_DREG_SLCTIS2	0x0E4
205  #define D40_DREG_SLCTIS3	0x0E8
206  #define D40_DREG_SLCTIS4	0x0EC
207  
208  #define D40_DREG_SLCEIS1	0x0F0
209  #define D40_DREG_SLCEIS2	0x0F4
210  #define D40_DREG_SLCEIS3	0x0F8
211  #define D40_DREG_SLCEIS4	0x0FC
212  
213  #define D40_DREG_FSESS1		0x100
214  #define D40_DREG_FSESS2		0x104
215  
216  #define D40_DREG_FSEBS1		0x108
217  #define D40_DREG_FSEBS2		0x10C
218  
219  #define D40_DREG_PSEG1		0x110
220  #define D40_DREG_PSEG2		0x114
221  #define D40_DREG_PSEG3		0x118
222  #define D40_DREG_PSEG4		0x11C
223  #define D40_DREG_PCEG1		0x120
224  #define D40_DREG_PCEG2		0x124
225  #define D40_DREG_PCEG3		0x128
226  #define D40_DREG_PCEG4		0x12C
227  #define D40_DREG_RSEG1		0x130
228  #define D40_DREG_RSEG2		0x134
229  #define D40_DREG_RSEG3		0x138
230  #define D40_DREG_RSEG4		0x13C
231  #define D40_DREG_RCEG1		0x140
232  #define D40_DREG_RCEG2		0x144
233  #define D40_DREG_RCEG3		0x148
234  #define D40_DREG_RCEG4		0x14C
235  
236  #define D40_DREG_PREFOT		0x15C
237  #define D40_DREG_EXTCFG		0x160
238  
239  #define D40_DREG_CPSEG1		0x200
240  #define D40_DREG_CPSEG2		0x204
241  #define D40_DREG_CPSEG3		0x208
242  #define D40_DREG_CPSEG4		0x20C
243  #define D40_DREG_CPSEG5		0x210
244  
245  #define D40_DREG_CPCEG1		0x220
246  #define D40_DREG_CPCEG2		0x224
247  #define D40_DREG_CPCEG3		0x228
248  #define D40_DREG_CPCEG4		0x22C
249  #define D40_DREG_CPCEG5		0x230
250  
251  #define D40_DREG_CRSEG1		0x240
252  #define D40_DREG_CRSEG2		0x244
253  #define D40_DREG_CRSEG3		0x248
254  #define D40_DREG_CRSEG4		0x24C
255  #define D40_DREG_CRSEG5		0x250
256  
257  #define D40_DREG_CRCEG1		0x260
258  #define D40_DREG_CRCEG2		0x264
259  #define D40_DREG_CRCEG3		0x268
260  #define D40_DREG_CRCEG4		0x26C
261  #define D40_DREG_CRCEG5		0x270
262  
263  #define D40_DREG_CFSESS1	0x280
264  #define D40_DREG_CFSESS2	0x284
265  #define D40_DREG_CFSESS3	0x288
266  
267  #define D40_DREG_CFSEBS1	0x290
268  #define D40_DREG_CFSEBS2	0x294
269  #define D40_DREG_CFSEBS3	0x298
270  
271  #define D40_DREG_CLCMIS1	0x300
272  #define D40_DREG_CLCMIS2	0x304
273  #define D40_DREG_CLCMIS3	0x308
274  #define D40_DREG_CLCMIS4	0x30C
275  #define D40_DREG_CLCMIS5	0x310
276  
277  #define D40_DREG_CLCICR1	0x320
278  #define D40_DREG_CLCICR2	0x324
279  #define D40_DREG_CLCICR3	0x328
280  #define D40_DREG_CLCICR4	0x32C
281  #define D40_DREG_CLCICR5	0x330
282  
283  #define D40_DREG_CLCTIS1	0x340
284  #define D40_DREG_CLCTIS2	0x344
285  #define D40_DREG_CLCTIS3	0x348
286  #define D40_DREG_CLCTIS4	0x34C
287  #define D40_DREG_CLCTIS5	0x350
288  
289  #define D40_DREG_CLCEIS1	0x360
290  #define D40_DREG_CLCEIS2	0x364
291  #define D40_DREG_CLCEIS3	0x368
292  #define D40_DREG_CLCEIS4	0x36C
293  #define D40_DREG_CLCEIS5	0x370
294  
295  #define D40_DREG_CPCMIS		0x380
296  #define D40_DREG_CPCICR		0x384
297  #define D40_DREG_CPCTIS		0x388
298  #define D40_DREG_CPCEIS		0x38C
299  
300  #define D40_DREG_SCCIDA1	0xE80
301  #define D40_DREG_SCCIDA2	0xE90
302  #define D40_DREG_SCCIDA3	0xEA0
303  #define D40_DREG_SCCIDA4	0xEB0
304  #define D40_DREG_SCCIDA5	0xEC0
305  
306  #define D40_DREG_SCCIDB1	0xE84
307  #define D40_DREG_SCCIDB2	0xE94
308  #define D40_DREG_SCCIDB3	0xEA4
309  #define D40_DREG_SCCIDB4	0xEB4
310  #define D40_DREG_SCCIDB5	0xEC4
311  
312  #define D40_DREG_PRSCCIDA	0xF80
313  #define D40_DREG_PRSCCIDB	0xF84
314  
315  #define D40_DREG_STFU		0xFC8
316  #define D40_DREG_ICFG		0xFCC
317  #define D40_DREG_PERIPHID0	0xFE0
318  #define D40_DREG_PERIPHID1	0xFE4
319  #define D40_DREG_PERIPHID2	0xFE8
320  #define D40_DREG_PERIPHID3	0xFEC
321  #define D40_DREG_CELLID0	0xFF0
322  #define D40_DREG_CELLID1	0xFF4
323  #define D40_DREG_CELLID2	0xFF8
324  #define D40_DREG_CELLID3	0xFFC
325  
326  /* LLI related structures */
327  
328  /**
329   * struct d40_phy_lli - The basic configuration register for each physical
330   * channel.
331   *
332   * @reg_cfg: The configuration register.
333   * @reg_elt: The element register.
334   * @reg_ptr: The pointer register.
335   * @reg_lnk: The link register.
336   *
337   * These registers are set up for both physical and logical transfers
338   * Note that the bit in each register means differently in logical and
339   * physical(standard) mode.
340   *
341   * This struct must be 16 bytes aligned, and only contain physical registers
342   * since it will be directly accessed by the DMA.
343   */
344  struct d40_phy_lli {
345  	u32 reg_cfg;
346  	u32 reg_elt;
347  	u32 reg_ptr;
348  	u32 reg_lnk;
349  };
350  
351  /**
352   * struct d40_phy_lli_bidir - struct for a transfer.
353   *
354   * @src: Register settings for src channel.
355   * @dst: Register settings for dst channel.
356   *
357   * All DMA transfers have a source and a destination.
358   */
359  
360  struct d40_phy_lli_bidir {
361  	struct d40_phy_lli	*src;
362  	struct d40_phy_lli	*dst;
363  };
364  
365  
366  /**
367   * struct d40_log_lli - logical lli configuration
368   *
369   * @lcsp02: Either maps to register lcsp0 if src or lcsp2 if dst.
370   * @lcsp13: Either maps to register lcsp1 if src or lcsp3 if dst.
371   *
372   * This struct must be 8 bytes aligned since it will be accessed directy by
373   * the DMA. Never add any none hw mapped registers to this struct.
374   */
375  
376  struct d40_log_lli {
377  	u32 lcsp02;
378  	u32 lcsp13;
379  };
380  
381  /**
382   * struct d40_log_lli_bidir - For both src and dst
383   *
384   * @src: pointer to src lli configuration.
385   * @dst: pointer to dst lli configuration.
386   *
387   * You always have a src and a dst when doing DMA transfers.
388   */
389  
390  struct d40_log_lli_bidir {
391  	struct d40_log_lli *src;
392  	struct d40_log_lli *dst;
393  };
394  
395  /**
396   * struct d40_log_lli_full - LCPA layout
397   *
398   * @lcsp0: Logical Channel Standard Param 0 - Src.
399   * @lcsp1: Logical Channel Standard Param 1 - Src.
400   * @lcsp2: Logical Channel Standard Param 2 - Dst.
401   * @lcsp3: Logical Channel Standard Param 3 - Dst.
402   *
403   * This struct maps to LCPA physical memory layout. Must map to
404   * the hw.
405   */
406  struct d40_log_lli_full {
407  	u32 lcsp0;
408  	u32 lcsp1;
409  	u32 lcsp2;
410  	u32 lcsp3;
411  };
412  
413  /**
414   * struct d40_def_lcsp - Default LCSP1 and LCSP3 settings
415   *
416   * @lcsp3: The default configuration for dst.
417   * @lcsp1: The default configuration for src.
418   */
419  struct d40_def_lcsp {
420  	u32 lcsp3;
421  	u32 lcsp1;
422  };
423  
424  /* Physical channels */
425  
426  enum d40_lli_flags {
427  	LLI_ADDR_INC	= 1 << 0,
428  	LLI_TERM_INT	= 1 << 1,
429  	LLI_CYCLIC	= 1 << 2,
430  	LLI_LAST_LINK	= 1 << 3,
431  };
432  
433  void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
434  		 u32 *src_cfg,
435  		 u32 *dst_cfg);
436  
437  void d40_log_cfg(struct stedma40_chan_cfg *cfg,
438  		 u32 *lcsp1,
439  		 u32 *lcsp2);
440  
441  int d40_phy_sg_to_lli(struct scatterlist *sg,
442  		      int sg_len,
443  		      dma_addr_t target,
444  		      struct d40_phy_lli *lli,
445  		      dma_addr_t lli_phys,
446  		      u32 reg_cfg,
447  		      struct stedma40_half_channel_info *info,
448  		      struct stedma40_half_channel_info *otherinfo,
449  		      unsigned long flags);
450  
451  /* Logical channels */
452  
453  int d40_log_sg_to_lli(struct scatterlist *sg,
454  		      int sg_len,
455  		      dma_addr_t dev_addr,
456  		      struct d40_log_lli *lli_sg,
457  		      u32 lcsp13, /* src or dst*/
458  		      u32 data_width1, u32 data_width2);
459  
460  void d40_log_lli_lcpa_write(struct d40_log_lli_full *lcpa,
461  			    struct d40_log_lli *lli_dst,
462  			    struct d40_log_lli *lli_src,
463  			    int next, unsigned int flags);
464  
465  void d40_log_lli_lcla_write(struct d40_log_lli *lcla,
466  			    struct d40_log_lli *lli_dst,
467  			    struct d40_log_lli *lli_src,
468  			    int next, unsigned int flags);
469  
470  #endif /* STE_DMA40_LLI_H */
471