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Searched refs:CS0 (Results 1 – 25 of 211) sorted by relevance

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/openbmc/u-boot/arch/arm/mach-omap2/omap3/
H A Dsdrc.c40 if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR) in is_mem_sdr()
55 size = get_sdr_cs_size(CS0); in make_cs1_contiguous()
170 write_sdrc_timings(CS0, sdrc_actim_base0, &timings); in do_sdrc_init()
184 timings.mcfg = readl(&sdrc_base->cs[CS0].mcfg), in do_sdrc_init()
185 timings.rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl); in do_sdrc_init()
188 timings.mr = readl(&sdrc_base->cs[CS0].mr); in do_sdrc_init()
201 size0 = get_sdr_cs_size(CS0); in dram_init()
222 size0 = get_sdr_cs_size(CS0); in dram_init_banksize()
241 do_sdrc_init(CS0, EARLY_INIT); in mem_init()
H A Demif4.c41 if (cs == CS0) in get_sdr_cs_size()
131 size0 = get_sdr_cs_size(CS0); in dram_init()
148 size0 = get_sdr_cs_size(CS0); in dram_init_banksize()
/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c206 [dq], CS0, (1 - ecc) * in ddr3_pbs_tx()
373 ddr3_pbs_write_pup_dqs_reg(CS0, pup, INIT_WL_DELAY); in ddr3_pbs_tx()
452 ddr3_pbs_write_pup_dqs_reg(CS0, in ddr3_tx_shift_dqs_adll_step_before_fail()
505 ddr3_pbs_write_pup_dqs_reg(CS0, pup * (1 - ecc) + ECC_PUP * ecc, in ddr3_tx_shift_dqs_adll_step_before_fail()
646 [dq], CS0, in ddr3_pbs_rx()
654 DQ_NUM, CS0, in ddr3_pbs_rx()
701 (PUP_DQS_RD, CS0, in ddr3_pbs_rx()
717 [dq], CS0, in ddr3_pbs_rx()
748 ddr3_write_pup_reg(PUP_DQS_RD, CS0, in ddr3_pbs_rx()
886 ddr3_write_pup_reg(PUP_DQS_RD, CS0, PUP_BC, 0, INIT_RL_DELAY); in ddr3_pbs_rx()
[all …]
/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-bus-iio-sx93246 SX9324 has 3 inputs, CS0, CS1 and CS2. Hardware layout
18 By default, during the first phase, [PH0], CS0 is measured,
21 [PH1], CS1 is measured, CS0 and CS2 are shield:
23 [PH2], CS2 is measured, CS0 and CS1 are shield:
H A Dsysfs-class-watchdog110 chip at CS0 after booting from the alternate
114 from (CS0->CS1, CS1->CS0) to (CS0->CS0,
119 the SoC is in normal mapping state (i.e. booted from CS0),
/openbmc/linux/drivers/staging/fbtft/
H A Dfb_agm1264k-fl.c32 #define CS0 gpio.aux[0] macro
101 if (!par->CS0) { in verify_gpios()
132 par->CS0 = gpio->gpio; in request_gpios_match()
184 gpiod_set_value(par->CS0, 0); in write_reg8_bus8()
188 gpiod_set_value(par->CS0, 1); in write_reg8_bus8()
387 gpiod_set_value(par->CS0, 0); in write_vmem()
/openbmc/u-boot/board/ccv/xpress/
H A Dimximage.cfg160 DATA 4 0x021b001c 0x02008032 /* MMDC0_MDSCR, MR2 write, CS0 */
161 DATA 4 0x021b001c 0x00008033 /* MMDC0_MDSCR, MR3 write, CS0 */
162 DATA 4 0x021b001c 0x00048031 /* MMDC0_MDSCR, MR1 write, CS0 */
163 DATA 4 0x021b001c 0x15208030 /* MMDC0_MDSCR, MR0 write, CS0 */
165 device on CS0 */
/openbmc/u-boot/doc/
H A DREADME.fsl-ddr31 |Controller | None | 2x1 lower | 2x1 upper | {CS0+CS1}, | {CS0+CS1+ |
32 |Interleaving | | {CS0+CS1} | {CS2+CS3} | {CS2+CS3} | CS2+CS3} |
37 | |CS0 Only| | | {CS0+CS1} | |
40 | |CS0 Only| | | {CS0+CS1} | |
43 | |CS0 Only| | | {CS0+CS1} | |
46 | | | | | {CS0+CS1} | |
49 interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1}
408 DDR Chip-Select Interleaving Mode: CS0+CS1
/openbmc/u-boot/board/freescale/mpc837xemds/
H A DREADME34 J10 removed, CS0 connect to NOR flash; when mounted, CS0 connect to NAND
55 0xfe00_0000 0xffff_ffff NOR Flash on CS0 32M
/openbmc/u-boot/board/sbc8548/
H A DREADME127 have U-Boot in the 8MB flash, tied to /CS0.
129 If you are running the default 8MB /CS0 settings but want to store an
141 Finally, if you are running the alternate 64MB /CS0 settings and want
176 JP12 CS0/CS6 swap see note[*] see note[*]
191 onto /CS0 and the SODIMM flash on /CS6 (default). When JP12
192 is jumpered parallel to the LBC-SDRAM, then /CS0 is for the
257 ff80_0000 ffff_ffff CS0 8 Boot flash (8MB)
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap2420-n8x0-common.dtsi48 ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */
56 reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
H A Ddra62x-j5eco-evm.dts46 ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */
50 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
H A Domap3-gta04a5one.dts44 ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */
55 reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
H A Ddm8148-evm.dts46 ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */
50 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
/openbmc/linux/arch/arm/boot/dts/intel/ixp/
H A Dintel-ixp42x-iomega-nas100d.dts93 /* The first 16MB region at CS0 on the expansion bus */
99 * mapped in at CS0.
/openbmc/u-boot/board/freescale/mpc8315erdb/
H A DREADME39 0xfe00_0000 0xfe7f_ffff NOR FLASH (CS0) 8M
41 When booting from NAND, NAND flash is CS0 and NOR flash
/openbmc/u-boot/board/LaCie/netspace_v2/
H A Dkwbimage.cfg123 # bit3-2: 00, CS0 hit selected
132 # bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
133 # bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
H A Dkwbimage-is2.cfg123 # bit3-2: 00, CS0 hit selected
132 # bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
133 # bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
H A Dkwbimage-ns2l.cfg123 # bit3-2: 00, CS0 hit selected
132 # bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
133 # bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
/openbmc/u-boot/board/cloudengines/pogo_e02/
H A Dkwbimage.cfg127 # bit3-2: 00, CS0 hit selected
139 # bit7-4: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
141 # bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
/openbmc/u-boot/board/iomega/iconnect/
H A Dkwbimage.cfg123 # bit3-2: 0x0, CS0 hit selected
135 # bit7-4: ODT0Rd, MODT[0] asserted during read from DRAM CS0
137 # bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
/openbmc/u-boot/board/Marvell/openrd/
H A Dkwbimage.cfg123 # bit3-2: 00, CS0 hit selected
135 # bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0
137 # bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0.
/openbmc/u-boot/board/LaCie/net2big_v2/
H A Dkwbimage.cfg123 # bit3-2: 00, CS0 hit selected
132 # bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
133 # bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
/openbmc/u-boot/board/keymile/km_arm/
H A Dkwbimage.cfg134 # bit3-2: 00, CS0 hit selected
143 # bit3-0: 0, ODT0Rd, MODT[0] asserted during read from DRAM CS0
144 # bit19-16:0, ODT0Wr, MODT[0] asserted during write to DRAM CS0
/openbmc/u-boot/board/raidsonic/ib62x0/
H A Dkwbimage.cfg124 # bit3-2: 0x0, CS0 hit selected
136 # bit7-4: ODT0Rd, MODT[0] asserted during read from DRAM CS0
138 # bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0

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