Home
last modified time | relevance | path

Searched refs:CRX_PHY_REG (Results 1 – 8 of 8) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_bist.c504 ddr3_tip_read_adll_value(0, rd_ctrl_adll, CRX_PHY_REG(cs), MASK_ALL_BITS); in mv_ddr_dm_vw_get()
598 subphy, DDR_PHY_DATA, CRX_PHY_REG(cs), in mv_ddr_dm_vw_get()
H A Dmv_ddr_regs.h411 #define CRX_PHY_REG(cs) (CRX_PHY_BASE + (cs) * 0x4) macro
H A Dddr3_training_ip_engine.c479 reg_data = CRX_PHY_REG(effective_cs); in ddr3_tip_ip_training()
1487 CRX_PHY_REG(effective_cs), in ddr3_tip_load_phy_values()
1509 CRX_PHY_REG(effective_cs), in ddr3_tip_load_phy_values()
H A Dddr3_training_pbs.c73 CRX_PHY_REG(effective_cs) : in ddr3_tip_pbs()
854 CRX_PHY_REG(effective_cs) : in ddr3_tip_pbs()
H A Dddr3_debug.c618 CRX_PHY_REG(csindex), in ddr3_tip_print_stability_log()
972 reg = (direction == 0) ? CTX_PHY_REG(cs) : CRX_PHY_REG(cs); in ddr3_tip_run_sweep_test()
H A Dddr3_training_centralization.c98 reg_phy_off = CRX_PHY_REG(effective_cs); in ddr3_tip_centralization()
H A Dddr3_training_leveling.c427 CRX_PHY_REG(0), in ddr3_tip_dynamic_per_bit_read_leveling()
663 CRX_PHY_REG(0), in ddr3_tip_dynamic_per_bit_read_leveling()
H A Dddr3_training.c1899 CRX_PHY_REG(effective_cs), phy_reg3_val)); in ddr3_tip_ddr3_reset_phy_regs()