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Searched refs:CR4_FSGSBASE_MASK (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/target/i386/
H A Dcpu.h256 #define CR4_FSGSBASE_MASK (1U << 16) macro
277 | CR4_FSGSBASE_MASK | CR4_PCIDE_MASK | CR4_OSXSAVE_MASK \
2721 reserved_bits |= CR4_FSGSBASE_MASK; in cr4_reserved_bits()
H A Dcpu.c7311 cr4 |= CR4_FSGSBASE_MASK; in x86_cpu_reset_hold()
/openbmc/qemu/target/i386/tcg/
H A Demit.c.inc3575 gen_helper_cr4_testbit(tcg_env, tcg_constant_i32(CR4_FSGSBASE_MASK));
4663 gen_helper_cr4_testbit(tcg_env, tcg_constant_i32(CR4_FSGSBASE_MASK));