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Searched refs:CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK (Results 1 – 16 of 16) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v7_0.c3856 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; in gfx_v7_0_init_gfx_cgpg()
H A Dgfx_v11_0.c4873 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); in gfx_v11_0_update_coarse_grain_clock_gating()
H A Dgfx_v9_0.c2679 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; in gfx_v9_0_init_gfx_power_gating()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2846 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000L macro
H A Dgfx_7_2_sh_mask.h3081 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 macro
H A Dgfx_8_1_sh_mask.h4217 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 macro
H A Dgfx_8_0_sh_mask.h3695 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h1220 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK … macro
H A Dgc_9_1_sh_mask.h1119 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK … macro
H A Dgc_9_2_1_sh_mask.h1086 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK … macro
H A Dgc_9_4_3_sh_mask.h1136 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK … macro
H A Dgc_9_4_2_sh_mask.h1719 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK … macro
H A Dgc_11_0_0_sh_mask.h6572 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK … macro
H A Dgc_10_1_0_sh_mask.h6708 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK … macro
H A Dgc_11_0_3_sh_mask.h7347 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK … macro
H A Dgc_10_3_0_sh_mask.h6974 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK … macro