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Searched refs:CP_ME_CNTL (Results 1 – 15 of 15) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c2222 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_pfp_cache_rs64()
2225 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_pfp_cache_rs64()
2231 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_pfp_cache_rs64()
2234 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_pfp_cache_rs64()
2345 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_me_cache_rs64()
2348 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_me_cache_rs64()
2354 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_me_cache_rs64()
2357 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_me_cache_rs64()
2505 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); in gfx_v11_0_config_gfx_rs64()
2506 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); in gfx_v11_0_config_gfx_rs64()
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H A Dgfx_v8_0.c4099 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0); in gfx_v8_0_cp_gfx_enable()
4100 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0); in gfx_v8_0_cp_gfx_enable()
4101 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0); in gfx_v8_0_cp_gfx_enable()
4103 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1); in gfx_v8_0_cp_gfx_enable()
4104 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1); in gfx_v8_0_cp_gfx_enable()
4105 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1); in gfx_v8_0_cp_gfx_enable()
H A Dsid.h1025 #define CP_ME_CNTL 0x21B6 macro
H A Dgfx_v9_0.c2963 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
2964 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
2965 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
H A Dgfx_v10_0.c5660 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); in gfx_v10_0_cp_gfx_enable()
5661 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); in gfx_v10_0_cp_gfx_enable()
5662 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); in gfx_v10_0_cp_gfx_enable()
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dni.c1451 WREG32(CP_ME_CNTL, 0); in cayman_cp_enable()
1455 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); in cayman_cp_enable()
1833 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); in cayman_gpu_soft_reset()
H A Drv770d.h335 #define CP_ME_CNTL 0x86D8 macro
H A Dnid.h318 #define CP_ME_CNTL 0x86D8 macro
H A Dsid.h1027 #define CP_ME_CNTL 0x86D8 macro
H A Dcikd.h1108 #define CP_ME_CNTL 0x86D8 macro
H A Dsi.c3462 WREG32(CP_ME_CNTL, 0); in si_cp_enable()
3466 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT)); in si_cp_enable()
3879 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in si_gpu_soft_reset()
4048 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in si_gpu_pci_config_reset()
H A Devergreen.c3020 WREG32(CP_ME_CNTL, cp_me); in evergreen_cp_start()
3911 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); in evergreen_gpu_soft_reset()
4021 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); in evergreen_gpu_pci_config_reset()
H A Drv770.c1084 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); in r700_cp_stop()
H A Devergreend.h461 #define CP_ME_CNTL 0x86D8 macro
H A Dcik.c3866 WREG32(CP_ME_CNTL, 0); in cik_cp_gfx_enable()
3870 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT)); in cik_cp_gfx_enable()
4947 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in cik_gpu_soft_reset()
5151 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in cik_gpu_pci_config_reset()