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Searched refs:CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2426 #define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x00800000L macro
H A Dgfx_7_2_sh_mask.h1229 #define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x800000 macro
H A Dgfx_8_1_sh_mask.h2093 #define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x800000 macro
H A Dgfx_8_0_sh_mask.h1569 #define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x800000 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h11072 #define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK … macro
H A Dgc_9_1_sh_mask.h12553 #define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK … macro
H A Dgc_9_2_1_sh_mask.h12357 #define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK … macro
H A Dgc_9_4_3_sh_mask.h14082 #define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK … macro
H A Dgc_9_4_2_sh_mask.h2373 #define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK … macro
H A Dgc_10_1_0_sh_mask.h18021 #define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK … macro
H A Dgc_10_3_0_sh_mask.h16285 #define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK … macro