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Searched refs:CP_HQD_PQ_CONTROL__PRIV_STATE_MASK (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v7_0.c2909 CP_HQD_PQ_CONTROL__PRIV_STATE_MASK | in gfx_v7_0_mqd_init()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h3359 #define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000 macro
H A Dgfx_8_1_sh_mask.h4497 #define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000 macro
H A Dgfx_8_0_sh_mask.h3975 #define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h12918 #define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK … macro
H A Dgc_9_1_sh_mask.h14222 #define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK … macro
H A Dgc_9_2_1_sh_mask.h14087 #define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK … macro
H A Dgc_9_4_3_sh_mask.h16452 #define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK … macro
H A Dgc_9_4_2_sh_mask.h4020 #define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK … macro
H A Dgc_11_0_0_sh_mask.h17399 #define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK … macro
H A Dgc_10_1_0_sh_mask.h20333 #define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK … macro
H A Dgc_11_0_3_sh_mask.h19638 #define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK … macro
H A Dgc_10_3_0_sh_mask.h18486 #define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK … macro