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Searched refs:CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_1_sh_mask.h4404 #define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8 macro
H A Dgfx_8_0_sh_mask.h3882 #define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h12762 #define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT … macro
H A Dgc_9_1_sh_mask.h14066 #define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h13931 #define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT … macro
H A Dgc_9_4_3_sh_mask.h16292 #define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h3862 #define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h24755 #define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h20167 #define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h27194 #define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h18322 #define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT … macro