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Searched refs:CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h2052 #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15 macro
H A Dgfx_8_1_sh_mask.h3106 #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15 macro
H A Dgfx_8_0_sh_mask.h2584 #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h629 #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT … macro
H A Dgc_9_1_sh_mask.h528 #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h517 #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT … macro
H A Dgc_9_4_3_sh_mask.h558 #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h1147 #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h6004 #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h6063 #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h6779 #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h6316 #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT … macro