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Searched refs:CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h2023 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x20 macro
H A Dgfx_8_1_sh_mask.h3077 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x20 macro
H A Dgfx_8_0_sh_mask.h2555 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x20 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h643 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK … macro
H A Dgc_9_1_sh_mask.h542 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK … macro
H A Dgc_9_2_1_sh_mask.h531 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK … macro
H A Dgc_9_4_3_sh_mask.h572 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK … macro
H A Dgc_9_4_2_sh_mask.h1161 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK … macro
H A Dgc_11_0_0_sh_mask.h6018 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK … macro
H A Dgc_10_1_0_sh_mask.h6077 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK … macro
H A Dgc_11_0_3_sh_mask.h6793 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK … macro
H A Dgc_10_3_0_sh_mask.h6330 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK … macro