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Searched refs:CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2091 #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x00000000 macro
H A Dgfx_7_2_sh_mask.h3200 #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0 macro
H A Dgfx_8_1_sh_mask.h4336 #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0 macro
H A Dgfx_8_0_sh_mask.h3814 #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h1315 #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT … macro
H A Dgc_9_1_sh_mask.h1214 #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h1181 #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT … macro
H A Dgc_9_4_3_sh_mask.h1231 #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h1814 #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h6801 #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h7067 #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT … macro