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Searched refs:CPU_LOG_MMU (Results 1 – 25 of 25) sorted by relevance

/openbmc/qemu/target/ppc/
H A Dmmu-booke.c39 qemu_log_mask(CPU_LOG_MMU, "%s: TLB %d address " TARGET_FMT_lx in ppcemb_tlb_check()
88 qemu_log_mask(CPU_LOG_MMU, in mmu40x_get_physical_address()
126 qemu_log_mask(CPU_LOG_MMU, "%s: access %s " TARGET_FMT_lx " => " in mmu40x_get_physical_address()
162 qemu_log_mask(CPU_LOG_MMU, "%s: TLB entry not found\n", __func__); in mmubooke_check_tlb()
170 qemu_log_mask(CPU_LOG_MMU, "%s: AS doesn't match\n", __func__); in mmubooke_check_tlb()
180 qemu_log_mask(CPU_LOG_MMU, "%s: good TLB!\n", __func__); in mmubooke_check_tlb()
184 qemu_log_mask(CPU_LOG_MMU, "%s: no prot match: %x\n", __func__, *prot); in mmubooke_check_tlb()
203 qemu_log_mask(CPU_LOG_MMU, in mmubooke_get_physical_address()
237 qemu_log_mask(CPU_LOG_MMU, "%s: TLB ADDR=0x" TARGET_FMT_lx in ppcmas_tlb_check()
341 qemu_log_mask(CPU_LOG_MMU, "%s: No TLB entry found for effective address " in mmubooke206_check_tlb()
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H A Dmmu_common.c43 qemu_log_mask(CPU_LOG_MMU, "%s: " TARGET_FMT_lx "\n", __func__, value); in ppc_store_sdr1()
106 qemu_log_mask(CPU_LOG_MMU, "TLB %d/%d %s [" TARGET_FMT_lx in ppc6xx_tlb_check()
113 qemu_log_mask(CPU_LOG_MMU, "TLB %d/%d %s " TARGET_FMT_lx " <> " in ppc6xx_tlb_check()
128 qemu_log_mask(CPU_LOG_MMU, "Bad RPN/WIMG/PP\n"); in ppc6xx_tlb_check()
137 qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n"); in ppc6xx_tlb_check()
141 qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n"); in ppc6xx_tlb_check()
146 qemu_log_mask(CPU_LOG_MMU, "found TLB at addr " HWADDR_FMT_plx in ppc6xx_tlb_check()
167 if (qemu_loglevel_mask(CPU_LOG_MMU)) { in ppc6xx_tlb_check()
199 qemu_log_mask(CPU_LOG_MMU, "%s: %cBAT v " TARGET_FMT_lx "\n", __func__, in get_bat_6xx_tlb()
213 qemu_log_mask(CPU_LOG_MMU, "%s: %cBAT%d v " TARGET_FMT_lx " BATu " in get_bat_6xx_tlb()
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H A Dmmu-hash32.c35 # define LOG_BATS(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)
122 qemu_log_mask(CPU_LOG_MMU, "direct store...\n"); in ppc_hash32_direct_store()
268 qemu_log_mask(CPU_LOG_MMU, "htab_base " HWADDR_FMT_plx in ppc_hash32_htab_lookup()
274 qemu_log_mask(CPU_LOG_MMU, "0 htab=" HWADDR_FMT_plx "/" HWADDR_FMT_plx in ppc_hash32_htab_lookup()
283 qemu_log_mask(CPU_LOG_MMU, "1 htab=" HWADDR_FMT_plx "/" HWADDR_FMT_plx in ppc_hash32_htab_lookup()
382 qemu_log_mask(CPU_LOG_MMU, in ppc_hash32_xlate()
391 qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n"); in ppc_hash32_xlate()
410 qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n"); in ppc_hash32_xlate()
H A Dmmu_helper.c72 qemu_log_mask(CPU_LOG_MMU, "TLB invalidate %d/%d " in ppc6xx_tlb_invalidate_virt2()
98 qemu_log_mask(CPU_LOG_MMU, "Set TLB %d/%d EPN " TARGET_FMT_lx " PTE0 " in ppc6xx_tlb_store()
158 qemu_log_mask(CPU_LOG_MMU, "Flush all BATs\n"); in do_invalidate_BAT()
160 qemu_log_mask(CPU_LOG_MMU, "Flush done\n"); in do_invalidate_BAT()
163 qemu_log_mask(CPU_LOG_MMU, "Flush BAT from " TARGET_FMT_lx in do_invalidate_BAT()
169 qemu_log_mask(CPU_LOG_MMU, "Flush done\n"); in do_invalidate_BAT()
176 qemu_log_mask(CPU_LOG_MMU, "Set %cBAT%d%c to " TARGET_FMT_lx " (" in dump_store_bat()
343 qemu_log_mask(CPU_LOG_MMU, in helper_store_sr()
437 qemu_log_mask(CPU_LOG_MMU, in helper_tlbie_isa300()
574 qemu_log_mask(CPU_LOG_MMU, "%s: EPN " TARGET_FMT_lx " " TARGET_FMT_lx in do_6xx_tlb()
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H A Dmmu-radix64.c150 qemu_log_mask(CPU_LOG_MMU, "%s for %s @0x%"VADDR_PRIx" cause %08x\n", in ppc_radix64_raise_si()
188 qemu_log_mask(CPU_LOG_MMU, "%s for %s @0x%"VADDR_PRIx" 0x%" in ppc_radix64_raise_hsi()
447 qemu_log_mask(CPU_LOG_MMU, "%s for %s @0x%"VADDR_PRIx in ppc_radix64_partition_scoped_xlate()
526 qemu_log_mask(CPU_LOG_MMU, "%s for %s @0x%"VADDR_PRIx in ppc_radix64_process_scoped_xlate()
815 qemu_log_mask(CPU_LOG_MMU, "%s for %s @0x%"VADDR_PRIx in ppc_radix64_xlate()
H A Dmmu-hash64.c44 # define LOG_SLB(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)
746 qemu_log_mask(CPU_LOG_MMU, in ppc_hash64_htab_lookup()
752 qemu_log_mask(CPU_LOG_MMU, in ppc_hash64_htab_lookup()
763 qemu_log_mask(CPU_LOG_MMU, in ppc_hash64_htab_lookup()
1134 qemu_log_mask(CPU_LOG_MMU, in ppc_hash64_xlate()
1152 qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n"); in ppc_hash64_xlate()
1183 qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n"); in ppc_hash64_xlate()
H A Dmisc_helper.c180 qemu_log_mask(CPU_LOG_MMU, "%s: " TARGET_FMT_lx "\n", __func__, val); in helper_store_ptcr()
H A Dexcp_helper.c166 if (!qemu_loglevel_mask(CPU_LOG_MMU)) { in ppc_excp_debug_sw_tlb()
/openbmc/qemu/target/microblaze/
H A Dmmu.c172 qemu_log_mask(CPU_LOG_MMU, in mmu_translate()
228 qemu_log_mask(CPU_LOG_MMU, "%s rn=%d=%x\n", __func__, rn, r); in mmu_read()
238 qemu_log_mask(CPU_LOG_MMU, in mmu_write()
H A Dhelper.c66 qemu_log_mask(CPU_LOG_MMU, "MMU map mmu=%d v=%x p=%x prot=%x\n", in mb_cpu_tlb_fill()
78 qemu_log_mask(CPU_LOG_MMU, "mmu=%d miss v=%" VADDR_PRIx "\n", in mb_cpu_tlb_fill()
/openbmc/qemu/target/hppa/
H A Dmem_helper.c673 qemu_log_mask(CPU_LOG_MMU, "FLUSH ALL TLB ENTRIES\n"); in HELPER()
732 qemu_log_mask(CPU_LOG_MMU, "PDC_BLOCK_TLB: PDC_BTLB_INFO\n"); in HELPER()
752 qemu_log_mask(CPU_LOG_MMU, "PDC_BLOCK_TLB: PDC_BTLB_INSERT " in HELPER()
778 qemu_log_mask(CPU_LOG_MMU, "PDC_BLOCK_TLB: PDC_BTLB_PURGE slot %d\n", in HELPER()
789 qemu_log_mask(CPU_LOG_MMU, "PDC_BLOCK_TLB: PDC_BTLB_PURGE_ALL\n"); in HELPER()
/openbmc/qemu/include/qemu/
H A Dlog.h28 #define CPU_LOG_MMU (1 << 12) macro
/openbmc/qemu/target/i386/
H A Dhelper.c118 qemu_log_mask(CPU_LOG_MMU, "A20 update: a20=%d\n", a20_state); in x86_cpu_set_a20()
135 qemu_log_mask(CPU_LOG_MMU, "CR0 update: CR0=0x%08x\n", new_cr0); in cpu_x86_update_cr0()
176 qemu_log_mask(CPU_LOG_MMU, in cpu_x86_update_cr3()
/openbmc/qemu/target/riscv/
H A Dcpu_helper.c1452 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", in riscv_cpu_tlb_fill()
1472 qemu_log_mask(CPU_LOG_MMU, in riscv_cpu_tlb_fill()
1485 qemu_log_mask(CPU_LOG_MMU, in riscv_cpu_tlb_fill()
1498 qemu_log_mask(CPU_LOG_MMU, in riscv_cpu_tlb_fill()
1523 qemu_log_mask(CPU_LOG_MMU, in riscv_cpu_tlb_fill()
1533 qemu_log_mask(CPU_LOG_MMU, in riscv_cpu_tlb_fill()
/openbmc/qemu/target/loongarch/tcg/
H A Dtlb_helper.c191 qemu_log_mask(CPU_LOG_MMU, "page size is 0\n"); in fill_tlb_entry()
494 qemu_log_mask(CPU_LOG_MMU, in loongarch_cpu_tlb_fill()
499 qemu_log_mask(CPU_LOG_MMU, in loongarch_cpu_tlb_fill()
/openbmc/qemu/target/openrisc/
H A Dmmu.c80 qemu_log_mask(CPU_LOG_MMU, in get_phys_mmu()
/openbmc/qemu/target/xtensa/
H A Dmmu_helper.c828 qemu_log_mask(CPU_LOG_MMU, "%s: autorefill(%08x): %08x -> %08x\n", in get_physical_addr_mmu()
878 qemu_log_mask(CPU_LOG_MMU, in get_pte()
882 qemu_log_mask(CPU_LOG_MMU, in get_pte()
893 qemu_log_mask(CPU_LOG_MMU, in get_pte()
H A Dhelper.c275 qemu_log_mask(CPU_LOG_MMU, "%s(%08" VADDR_PRIx in xtensa_cpu_tlb_fill()
/openbmc/qemu/target/tricore/
H A Dhelper.c80 qemu_log_mask(CPU_LOG_MMU, "%s address=0x%" VADDR_PRIx " ret %d physical " in tricore_cpu_tlb_fill()
/openbmc/qemu/target/s390x/tcg/
H A Dexcp_helper.c151 qemu_log_mask(CPU_LOG_MMU, "%s: addr 0x%" VADDR_PRIx " rw %d mmu_idx %d\n", in s390_cpu_tlb_fill()
177 qemu_log_mask(CPU_LOG_MMU, in s390_cpu_tlb_fill()
/openbmc/qemu/util/
H A Dlog.c481 { CPU_LOG_MMU, "mmu",
/openbmc/qemu/target/mips/tcg/sysemu/
H A Dtlb_helper.c922 qemu_log_mask(CPU_LOG_MMU, in mips_cpu_tlb_fill()
927 qemu_log_mask(CPU_LOG_MMU, in mips_cpu_tlb_fill()
/openbmc/qemu/target/sparc/
H A Dmmu_helper.c228 qemu_log_mask(CPU_LOG_MMU, in sparc_cpu_tlb_fill()
/openbmc/qemu/target/arm/
H A Dptw.c3523 qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32 in get_phys_addr_nogpc()
/openbmc/qemu/accel/tcg/
H A Dcputlb.c69 qemu_log_mask(CPU_LOG_MMU, "%s: " fmt, __func__, \